Use `gdb_report_register_access_error enable`

diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index f420417dcd505e5d47c03040bef6a9dc4ada7c20..083794fc14906a9fd9b133810371ba373bc20fbe 100644 (file)
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -11,6 +11,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 114d5b880b953861066d045b20112535226c9477..ef8bab10bff9d2c204638b60ab3f1065a5f100e1 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -14,6 +14,7 @@ target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.

diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 159a70fac42c7ffcaa6af1f1371ef43f0f73fdce..d8bd27e903aa333b4bf7b5d2cf970fd367404b64 100644 (file)
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.

diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 8f21b4776cb5728e65a8d05cf432b98a5932afbc..333c82e4706dd1eca8393180ca731ffe6dd7276b 100644 (file)
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -17,6 +17,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
 #-rtos riscv
 
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
 riscv expose_csrs 2288