add first unit test for simple-v

diff --git a/env b/env
index 4c356d46aace73c1562816a41e0f63948bdb0497..68cad7baf3ed0a4553fffd14726d24519ee1296a 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 4c356d46aace73c1562816a41e0f63948bdb0497
+Subproject commit 68cad7baf3ed0a4553fffd14726d24519ee1296a

diff --git a/isa/Makefile b/isa/Makefile
index 4e1ba20d2a07668719949b1ccc28d08dbffa24d3..a3a5ee59308bdad38e63a50bf865018822f73b56 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -8,6 +8,7 @@ src_dir := .
 
 ifeq ($(XLEN),64)
 include $(src_dir)/rv64ui/Makefrag
+include $(src_dir)/rv64ui/Makefrag.sv
 include $(src_dir)/rv64uc/Makefrag
 include $(src_dir)/rv64um/Makefrag
 include $(src_dir)/rv64ua/Makefrag
@@ -54,11 +55,11 @@ vpath %.S $(src_dir)
 define compile_template
 
 $$($(1)_p_tests): $(1)-p-%: $(1)/%.S
-       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -I$(src_dir)/macros/simplev -T$(src_dir)/../env/p/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_p_tests)
 
 $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
-       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -I$(src_dir)/macros/simplev -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
 $(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
new file mode 100644 (file)
index 0000000..fb26814
--- /dev/null
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -0,0 +1,4 @@
+#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec, packed) \
+  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, active) \
+  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
new file mode 100644 (file)
index 0000000..1ad8fe1
--- /dev/null
+++ b/isa/rv64ui/Makefrag.sv
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv64ui SV tests
+#-----------------------------------------------------------------------
+
+rv64ui_sv_tests = \
+       sv_addi \
+
+rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
+rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sv_tests))
+
+spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
new file mode 100644 (file)
index 0000000..b6493bc
--- /dev/null
+++ b/isa/rv64ui/sv_addi.S
@@ -0,0 +1,48 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+        csrrw   x0, 0x4f2, 2
+        la      x1, testdata
+        lw      x2, 0(x1)
+        la      x1, (testdata+8)
+        lw      x3, 0(x1)
+        li      x1, SV_REG_CSR(1, 2, 0, 2, 1, 0)
+        csrrw   x0, 0x4c0, x1
+        csrrw   x0, 0x4f0, 2
+        addi    x2, x2, 1         # Should be 42 into $2.
+        csrrwi  x0, 0x4f2, 0
+        csrrwi  x0, 0x4c0, 0
+        csrrwi  x0, 0x4f0, 0
+        li      x1, 42        # Desired result 1
+        bne     x2, x1, fail  # Fail out if doesn't match.
+        li      x1, 43        # Desired result 2
+        bne     x3, x1, fail  # Fail out if doesn't match.
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 41
+        .dword 42
+        .dword 43
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+