HOST_COMP = gcc $(HOST_OPTS)
RISCV_GCC = riscv-gcc
-RISCV_GCC_OPTS = -std=gnu99 -DSET_STATS -O2 -nostdlib -nostartfiles -ffast-math
+RISCV_GCC_OPTS = -Wa,-march=RVIMAFDXhwacha -std=gnu99 -O2 -nostdlib -nostartfiles -ffast-math
RISCV_LINK = riscv-gcc -T $(bmarkdir)/common/test.ld
RISCV_LINK_MT = riscv-gcc -T $(bmarkdir)/common/test-mt.ld
RISCV_LINK_OPTS = -lc
+#include "pcr.h"
+
.data
.globl _heapend
.globl environ
li x31,0
# enable fp
- mfpcr x1,cr0
- ori x1,x1,0x2
- mtpcr x1,cr0
+ setpcr status, SR_EF
# enable vec
- mfpcr x1,cr0
- ori x1,x1,0x4
- mtpcr x1,cr0
+ setpcr t0, status, SR_EV
## if that didn't stick, we don't have an FPU, so don't initialize it
- mfpcr x1,cr0
- andi x1,x1,0x2
- beqz x1,1f
+ and t0, t0, SR_EF
+ beqz t0, 1f
- mtfsr x0
- mxtf.s f0, x0
- mxtf.s f1, x0
- mxtf.s f2, x0
- mxtf.s f3, x0
- mxtf.s f4, x0
- mxtf.s f5, x0
- mxtf.s f6, x0
- mxtf.s f7, x0
- mxtf.s f8, x0
- mxtf.s f9, x0
- mxtf.s f10,x0
- mxtf.s f11,x0
- mxtf.s f12,x0
- mxtf.s f13,x0
- mxtf.s f14,x0
- mxtf.s f15,x0
- mxtf.s f16,x0
- mxtf.s f17,x0
- mxtf.s f18,x0
- mxtf.s f19,x0
- mxtf.s f20,x0
- mxtf.s f21,x0
- mxtf.s f22,x0
- mxtf.s f23,x0
- mxtf.s f24,x0
- mxtf.s f25,x0
- mxtf.s f26,x0
- mxtf.s f27,x0
- mxtf.s f28,x0
- mxtf.s f29,x0
- mxtf.s f30,x0
- mxtf.s f31,x0
+ fssr x0
+ fmv.s.x f0, x0
+ fmv.s.x f1, x0
+ fmv.s.x f2, x0
+ fmv.s.x f3, x0
+ fmv.s.x f4, x0
+ fmv.s.x f5, x0
+ fmv.s.x f6, x0
+ fmv.s.x f7, x0
+ fmv.s.x f8, x0
+ fmv.s.x f9, x0
+ fmv.s.x f10,x0
+ fmv.s.x f11,x0
+ fmv.s.x f12,x0
+ fmv.s.x f13,x0
+ fmv.s.x f14,x0
+ fmv.s.x f15,x0
+ fmv.s.x f16,x0
+ fmv.s.x f17,x0
+ fmv.s.x f18,x0
+ fmv.s.x f19,x0
+ fmv.s.x f20,x0
+ fmv.s.x f21,x0
+ fmv.s.x f22,x0
+ fmv.s.x f23,x0
+ fmv.s.x f24,x0
+ fmv.s.x f25,x0
+ fmv.s.x f26,x0
+ fmv.s.x f27,x0
+ fmv.s.x f28,x0
+ fmv.s.x f29,x0
+ fmv.s.x f30,x0
+ fmv.s.x f31,x0
1:
+
# get core id and number of cores
- mfpcr a0,cr10
+ mfpcr a0,hartid
lw a1, 4(zero)
slli a2, a0, 13
+#include "pcr.h"
+
.data
.globl _heapend
.globl environ
li x31,0
# enable fp
- mfpcr x1,cr0
- ori x1,x1,0x2
- mtpcr x1,cr0
+ setpcr status, SR_EF
# enable vec
- mfpcr x1,cr0
- ori x1,x1,0x4
- mtpcr x1,cr0
+ setpcr t0, status, SR_EV
## if that didn't stick, we don't have an FPU, so don't initialize it
- mfpcr x1,cr0
- andi x1,x1,0x2
- beqz x1,1f
+ and t0, t0, SR_EF
+ beqz t0, 1f
- mtfsr x0
- mxtf.s f0, x0
- mxtf.s f1, x0
- mxtf.s f2, x0
- mxtf.s f3, x0
- mxtf.s f4, x0
- mxtf.s f5, x0
- mxtf.s f6, x0
- mxtf.s f7, x0
- mxtf.s f8, x0
- mxtf.s f9, x0
- mxtf.s f10,x0
- mxtf.s f11,x0
- mxtf.s f12,x0
- mxtf.s f13,x0
- mxtf.s f14,x0
- mxtf.s f15,x0
- mxtf.s f16,x0
- mxtf.s f17,x0
- mxtf.s f18,x0
- mxtf.s f19,x0
- mxtf.s f20,x0
- mxtf.s f21,x0
- mxtf.s f22,x0
- mxtf.s f23,x0
- mxtf.s f24,x0
- mxtf.s f25,x0
- mxtf.s f26,x0
- mxtf.s f27,x0
- mxtf.s f28,x0
- mxtf.s f29,x0
- mxtf.s f30,x0
- mxtf.s f31,x0
+ fssr x0
+ fmv.s.x f0, x0
+ fmv.s.x f1, x0
+ fmv.s.x f2, x0
+ fmv.s.x f3, x0
+ fmv.s.x f4, x0
+ fmv.s.x f5, x0
+ fmv.s.x f6, x0
+ fmv.s.x f7, x0
+ fmv.s.x f8, x0
+ fmv.s.x f9, x0
+ fmv.s.x f10,x0
+ fmv.s.x f11,x0
+ fmv.s.x f12,x0
+ fmv.s.x f13,x0
+ fmv.s.x f14,x0
+ fmv.s.x f15,x0
+ fmv.s.x f16,x0
+ fmv.s.x f17,x0
+ fmv.s.x f18,x0
+ fmv.s.x f19,x0
+ fmv.s.x f20,x0
+ fmv.s.x f21,x0
+ fmv.s.x f22,x0
+ fmv.s.x f23,x0
+ fmv.s.x f24,x0
+ fmv.s.x f25,x0
+ fmv.s.x f26,x0
+ fmv.s.x f27,x0
+ fmv.s.x f28,x0
+ fmv.s.x f29,x0
+ fmv.s.x f30,x0
+ fmv.s.x f31,x0
1:
# only allow core 0 to proceed
-1:mfpcr a0, cr10
+1:mfpcr a0, hartid
bnez a0, 1b
la sp,stacktop
+// See LICENSE for license details.
+
#ifndef _RISCV_PCR_H
#define _RISCV_PCR_H
-#define SR_ET 0x00000001
-#define SR_EF 0x00000002
-#define SR_EV 0x00000004
-#define SR_EC 0x00000008
-#define SR_PS 0x00000010
-#define SR_S 0x00000020
-#define SR_U64 0x00000040
-#define SR_S64 0x00000080
-#define SR_VM 0x00000100
+#define SR_S 0x00000001
+#define SR_PS 0x00000002
+#define SR_EI 0x00000004
+#define SR_PEI 0x00000008
+#define SR_EF 0x00000010
+#define SR_U64 0x00000020
+#define SR_S64 0x00000040
+#define SR_VM 0x00000080
+#define SR_EV 0x00000100
#define SR_IM 0x00FF0000
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
+#define SR_IP 0xFF000000
+#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
#define SR_IM_SHIFT 16
+#define SR_IP_SHIFT 24
-#define PCR_SR 0
-#define PCR_EPC 1
-#define PCR_BADVADDR 2
-#define PCR_EVEC 3
-#define PCR_COUNT 4
-#define PCR_COMPARE 5
-#define PCR_CAUSE 6
-#define PCR_PTBR 7
-#define PCR_SEND_IPI 8
-#define PCR_CLR_IPI 9
-#define PCR_COREID 10
-#define PCR_IMPL 11
-#define PCR_K0 12
-#define PCR_K1 13
+#define PCR_SUP0 0
+#define PCR_SUP1 1
+#define PCR_EPC 2
+#define PCR_BADVADDR 3
+#define PCR_PTBR 4
+#define PCR_ASID 5
+#define PCR_COUNT 6
+#define PCR_COMPARE 7
+#define PCR_EVEC 8
+#define PCR_CAUSE 9
+#define PCR_SR 10
+#define PCR_HARTID 11
+#define PCR_IMPL 12
+#define PCR_FATC 13
+#define PCR_SEND_IPI 14
+#define PCR_CLR_IPI 15
#define PCR_VECBANK 18
#define PCR_VECCFG 19
#define PCR_RESET 29
#define PCR_TOHOST 30
#define PCR_FROMHOST 31
+#define IRQ_COP 2
#define IRQ_IPI 5
+#define IRQ_HOST 6
#define IRQ_TIMER 7
+#define IMPL_SPIKE 1
+#define IMPL_ROCKET 2
+
#define CAUSE_MISALIGNED_FETCH 0
#define CAUSE_FAULT_FETCH 1
#define CAUSE_ILLEGAL_INSTRUCTION 2
#define CAUSE_VECTOR_FAULT_LOAD 30
#define CAUSE_VECTOR_FAULT_STORE 31
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Entry is a page Table descriptor
+#define PTE_T 0x002 // Entry is a page Table, not a terminal node
+#define PTE_G 0x004 // Global
+#define PTE_UR 0x008 // User Write permission
+#define PTE_UW 0x010 // User Read permission
+#define PTE_UX 0x020 // User eXecute permission
+#define PTE_SR 0x040 // Supervisor Read permission
+#define PTE_SW 0x080 // Supervisor Write permission
+#define PTE_SX 0x100 // Supervisor eXecute permission
+#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
+
#ifdef __riscv
-#define ASM_CR(r) _ASM_CR(r)
-#define _ASM_CR(r) cr##r
+#ifdef __riscv64
+# define RISCV_PGLEVELS 3
+# define RISCV_PGSHIFT 13
+#else
+# define RISCV_PGLEVELS 2
+# define RISCV_PGSHIFT 12
+#endif
+#define RISCV_PGLEVEL_BITS 10
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
#ifndef __ASSEMBLER__
asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
__tmp; })
+#define rdcycle() ({ unsigned long __tmp; \
+ asm volatile ("rdcycle %0" : "=r"(__tmp)); \
+ __tmp; })
+
#endif
#endif
+++ /dev/null
- .file 1 "syscalls.c"
- .section .mdebug.abi64
- .previous
- .section .rodata.str1.8,"aMS",@progbits,1
- .align 3
-$LC0:
- .ascii "0123456789abcdef\000"
- .text
- .align 2
- .ent printnum
- .type printnum, @function
-printnum:
- .frame x30,64,x1 # vars= 0, regs= 7/0, args= 0
- .mask 0x03f00002,-8
- .fmask 0x00000000,0
- add x30,x30,-64
- sd x22,32(x30)
- sll x22,x7,32
- srl x22,x22,32
- sd x24,48(x30)
- sd x23,40(x30)
- sd x21,24(x30)
- sd x20,16(x30)
- sd x25,56(x30)
- sd x1,8(x30)
- move x23,x6
- move x20,x4
- move x21,x5
- move x24,x9
- bleu x22,x6,$L2
- addw x8,x8,-1
- move x25,x8
- ble x8,x0,$L4
-$L6:
- addw x25,x25,-1
- move x4,x24
- move x5,x21
- jalr x20
- bne x25,x0,$L6
-$L4:
- lui x2,%hi($LC0)
- add x2,x2,%lo($LC0)
- remu x22,x23,x22
- add x22,x22,x2
- lb x4,0(x22)
- move x5,x21
- move x19,x20
- ld x25,56(x30)
- ld x24,48(x30)
- ld x23,40(x30)
- ld x22,32(x30)
- ld x21,24(x30)
- ld x20,16(x30)
- ld x1,8(x30)
- add x30,x30,64
- jr x19
-$L2:
- addw x8,x8,-1
- divu x6,x6,x22
- jal printnum
- j $L4
- .end printnum
- .size printnum, .-printnum
- .align 2
- .ent getuint
- .type getuint, @function
-getuint:
- .frame x30,0,x1 # vars= 0, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- slt x2,x5,2
- bne x2,x0,$L10
-$L13:
- ld x2,0(x4)
- add x3,x2,8
- sd x3,0(x4)
- ld x2,0(x2)
- ret
-$L10:
- bne x5,x0,$L13
- ld x3,0(x4)
- lwu x2,0(x3)
- add x3,x3,8
- sd x3,0(x4)
- ret
- .end getuint
- .size getuint, .-getuint
- .align 2
- .globl putchar
- .ent putchar
- .type putchar, @function
-putchar:
- .frame x30,64,x1 # vars= 64, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- li x2,-1 # 0xffffffffffffffff
- add x30,x30,-64
- lui x3,%hi(buflen.1596)
- beq x4,x2,$L21
- lw x5,%lo(buflen.1596)(x3)
- lui x2,%hi(buf.1595)
- add x2,x2,%lo(buf.1595)
- add x6,x2,x5
- sb x4,0(x6)
- addw x5,x5,1
- li x4,64 # 0x40
- sw x5,%lo(buflen.1596)(x3)
- beq x5,x4,$L15
- move x2,x0
- add x30,x30,64
- j x1
-$L21:
- lui x2,%hi(buf.1595)
- add x2,x2,%lo(buf.1595)
-$L15:
- lw x4,%lo(buflen.1596)(x3)
- li x5,4 # 0x4
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x5,0(x30)
- li x5,1 # 0x1
- sd x5,8(x30)
- sd x2,16(x30)
- sd x4,24(x30)
- fence
- #APP
- # 45 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L17:
- #APP
- # 46 "syscalls.c" 1
- mfpcr x2,cr31
- # 0 "" 2
- #NO_APP
- beq x2,x0,$L17
- move x2,x0
- sw x0,%lo(buflen.1596)(x3)
- add x30,x30,64
- j x1
- .end putchar
- .size putchar, .-putchar
- .align 2
- .globl exit
- .ent exit
- .type exit, @function
-exit:
- .frame x30,64,x1 # vars= 64, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- add x30,x30,-64
- li x2,1 # 0x1
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x2,0(x30)
- sd x4,8(x30)
- fence
- #APP
- # 12 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L23:
- j $L23
- .end exit
- .size exit, .-exit
- .align 2
- .globl printstr
- .ent printstr
- .type printstr, @function
-printstr:
- .frame x30,80,x1 # vars= 64, regs= 1/0, args= 0
- .mask 0x00000002,-8
- .fmask 0x00000000,0
- add x30,x30,-80
- li x3,4 # 0x4
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x3,0(x30)
- li x3,1 # 0x1
- sd x3,8(x30)
- sd x1,72(x30)
- sd x4,16(x30)
- jal strlen
- sd x2,24(x30)
- fence
- #APP
- # 24 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L25:
- #APP
- # 25 "syscalls.c" 1
- mfpcr x2,cr31
- # 0 "" 2
- #NO_APP
- beq x2,x0,$L25
- ld x1,72(x30)
- add x30,x30,80
- j x1
- .end printstr
- .size printstr, .-printstr
- .align 2
- .globl printhex
- .ent printhex
- .type printhex, @function
-printhex:
- .frame x30,48,x1 # vars= 32, regs= 1/0, args= 0
- .mask 0x00000002,-8
- .fmask 0x00000000,0
- add x30,x30,-48
- sd x1,40(x30)
- add x2,x30,15
- add x7,x30,-1
-$L29:
- and x3,x4,15
- sltu x6,x3,10
- li x5,87 # 0x57
- beq x6,x0,$L28
- li x5,48 # 0x30
-$L28:
- add x3,x5,x3
- sb x3,0(x2)
- add x2,x2,-1
- srl x4,x4,4
- bne x2,x7,$L29
- move x4,x30
- sb x0,16(x30)
- jal printstr
- ld x1,40(x30)
- add x30,x30,48
- j x1
- .end printhex
- .size printhex, .-printhex
- .section .rodata.str1.8
- .align 3
-$LC1:
- .ascii "(null)\000"
- .text
- .align 2
- .globl vprintfmt
- .ent vprintfmt
- .type vprintfmt, @function
-vprintfmt:
- .frame x30,112,x1 # vars= 32, regs= 10/0, args= 0
- .mask 0x2ff00002,-8
- .fmask 0x00000000,0
- add x30,x30,-112
- sd x25,80(x30)
- lui x25,%hi($L53)
- sd x26,88(x30)
- sd x24,72(x30)
- sd x23,64(x30)
- sd x22,56(x30)
- sd x21,48(x30)
- sd x20,40(x30)
- sd x29,104(x30)
- sd x27,96(x30)
- sd x1,32(x30)
- move x21,x4
- move x20,x5
- move x23,x6
- sd x7,0(x30)
- li x22,37 # 0x25
- add x25,x25,%lo($L53)
- li x24,-1 # 0xffffffffffffffff
- lui x26,%hi($LC1)
- j $L84
-$L35:
- beq x2,x0,$L32
- move x5,x20
- add x23,x23,1
- jalr x21
-$L84:
- lbu x4,0(x23)
- move x2,x4
- bne x4,x22,$L35
- ld x2,0(x30)
- add x6,x23,1
- move x7,x6
- li x27,32 # 0x20
- sd x0,8(x30)
- li x3,-1 # 0xffffffffffffffff
- li x29,-1 # 0xffffffffffffffff
- move x5,x0
-$L85:
- lbu x4,0(x7)
- add x23,x7,1
- addw x8,x4,-35
- and x9,x8,0xff
- sltu x9,x9,86
- bne x9,x0,$L90
-$L38:
- li x4,37 # 0x25
- move x5,x20
- sd x2,0(x30)
- move x23,x6
- jalr x21
- j $L84
-$L32:
- ld x1,32(x30)
- ld x29,104(x30)
- ld x27,96(x30)
- ld x26,88(x30)
- ld x25,80(x30)
- ld x24,72(x30)
- ld x23,64(x30)
- ld x22,56(x30)
- ld x21,48(x30)
- ld x20,40(x30)
- add x30,x30,112
- j x1
-$L90:
- and x8,x8,0xff
- sll x8,x8,3
- add x8,x25,x8
- ld x8,0(x8)
- j x8
- .section .rodata
- .align 3
- .align 2
-$L53:
- .dword $L39
- .dword $L38
- .dword $L40
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L41
- .dword $L38
- .dword $L38
- .dword $L42
- .dword $L43
- .dword $L38
- .dword $L74
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L45
- .dword $L46
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L47
- .dword $L38
- .dword $L38
- .dword $L48
- .dword $L49
- .dword $L38
- .dword $L38
- .dword $L50
- .dword $L38
- .dword $L51
- .dword $L38
- .dword $L38
- .dword $L52
- .text
-$L52:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,16 # 0x10
-$L73:
- move x4,x21
- move x5,x20
- move x8,x29
- move x9,x27
- jal printnum
- j $L84
-$L39:
- li x4,1 # 0x1
- move x7,x23
- sd x4,8(x30)
- j $L85
-$L40:
- move x5,x20
- sd x2,0(x30)
- jalr x21
- j $L84
-$L41:
- lw x3,0(x2)
- move x7,x23
- add x2,x2,8
-$L54:
- bge x29,x0,$L85
- move x29,x3
- li x3,-1 # 0xffffffffffffffff
- j $L85
-$L42:
- move x7,x23
- li x27,45 # 0x2d
- j $L85
-$L43:
- blt x29,x0,$L91
- move x7,x23
- j $L85
-$L74:
- move x7,x23
- li x27,48 # 0x30
- j $L85
-$L44:
- lb x8,1(x7)
- addw x3,x4,-48
- move x7,x23
- addw x4,x8,-48
- sltu x4,x4,10
- beq x4,x0,$L54
-$L55:
- add x7,x7,1
- lb x4,0(x7)
- sllw x9,x3,1
- sllw x3,x3,3
- addw x3,x9,x3
- addw x9,x4,-48
- addw x3,x3,x8
- sltu x9,x9,10
- addw x3,x3,-48
- move x8,x4
- bne x9,x0,$L55
- j $L54
-$L45:
- lw x4,0(x2)
- add x2,x2,8
- move x5,x20
- sd x2,0(x30)
- jalr x21
- j $L84
-$L46:
- slt x3,x5,2
- bne x3,x0,$L69
-$L88:
- add x3,x2,8
- sd x3,0(x30)
- ld x6,0(x2)
- blt x6,x0,$L72
-$L89:
- li x7,10 # 0xa
- j $L73
-$L47:
- addw x5,x5,1
- move x7,x23
- j $L85
-$L48:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,8 # 0x8
- j $L73
-$L49:
- sd x2,0(x30)
- li x4,48 # 0x30
- move x5,x20
- jalr x21
- li x4,120 # 0x78
- move x5,x20
- jalr x21
- ld x2,0(x30)
- li x7,16 # 0x10
- add x3,x2,8
- sd x3,0(x30)
- ld x6,0(x2)
- j $L73
-$L50:
- add x4,x2,8
- sd x4,0(x30)
- ld x2,0(x2)
- sd x2,16(x30)
- beq x2,x0,$L92
-$L58:
- ble x29,x0,$L59
- li x2,45 # 0x2d
- beq x27,x2,$L59
- ld x4,16(x30)
- move x5,x3
- sd x3,24(x30)
- jal strnlen
- sllw x2,x2,0
- subw x2,x29,x2
- move x29,x2
- ld x3,24(x30)
- ble x2,x0,$L59
- move x29,x2
-$L60:
- sd x3,24(x30)
- move x4,x27
- move x5,x20
- addw x29,x29,-1
- jalr x21
- ld x3,24(x30)
- bne x29,x0,$L60
-$L59:
- ld x2,16(x30)
- lb x4,0(x2)
- add x27,x2,1
- beq x4,x0,$L62
-$L80:
- blt x3,x0,$L67
- addw x2,x3,-1
- move x3,x2
- beq x2,x24,$L62
-$L67:
- ld x2,8(x30)
- beq x2,x0,$L63
- addw x2,x4,-32
- sltu x2,x2,95
- beq x2,x0,$L93
-$L63:
- sd x3,24(x30)
- move x5,x20
- jalr x21
- ld x3,24(x30)
-$L64:
- lb x4,0(x27)
- addw x29,x29,-1
- add x27,x27,1
- bne x4,x0,$L80
-$L62:
- ble x29,x0,$L84
-$L79:
- addw x29,x29,-1
- li x4,32 # 0x20
- move x5,x20
- jalr x21
- bne x29,x0,$L79
- j $L84
-$L51:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,10 # 0xa
- j $L73
-$L93:
- sd x3,24(x30)
- li x4,63 # 0x3f
- move x5,x20
- jalr x21
- ld x3,24(x30)
- j $L64
-$L91:
- move x7,x23
- move x29,x0
- j $L85
-$L92:
- add x2,x26,%lo($LC1)
- sd x2,16(x30)
- j $L58
-$L72:
- sd x6,24(x30)
- li x4,45 # 0x2d
- move x5,x20
- jalr x21
- ld x6,24(x30)
- li x7,10 # 0xa
- sub x6,zero,x6
- j $L73
-$L69:
- bne x5,x0,$L88
- lw x6,0(x2)
- add x2,x2,8
- sd x2,0(x30)
- bge x6,x0,$L89
- j $L72
- .end vprintfmt
- .size vprintfmt, .-vprintfmt
- .align 2
- .globl printf
- .ent printf
- .type printf, @function
-printf:
- .frame x30,96,x1 # vars= 16, regs= 1/0, args= 0
- .mask 0x00000002,-72
- .fmask 0x00000000,0
- add x30,x30,-96
- add x2,x30,40
- move x3,x4
- lui x4,%hi(putchar)
- sd x5,40(x30)
- sd x6,48(x30)
- sd x7,56(x30)
- add x4,x4,%lo(putchar)
- move x5,x0
- move x6,x3
- move x7,x2
- sd x1,24(x30)
- sd x8,64(x30)
- sd x9,72(x30)
- sd x10,80(x30)
- sd x11,88(x30)
- sd x2,0(x30)
- jal vprintfmt
- li x4,-1 # 0xffffffffffffffff
- jal putchar
- ld x1,24(x30)
- move x2,x0
- add x30,x30,96
- j x1
- .end printf
- .size printf, .-printf
- .local buflen.1596
- .comm buflen.1596,4,4
- .local buf.1595
- .comm buf.1595,64,8
- .ident "GCC: (GNU) 4.6.1"
#include <stdint.h>
#include <string.h>
#include <stdarg.h>
+#include <machine/syscall.h>
#include "pcr.h"
void exit(int code)
{
volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 1;
+ magic_mem[0] = SYS_exit;
magic_mem[1] = code;
__sync_synchronize();
mtpcr(PCR_TOHOST, (long)magic_mem);
void printstr(const char* s)
{
volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 4;
+ magic_mem[0] = SYS_write;
magic_mem[1] = 1;
magic_mem[2] = (unsigned long)s;
magic_mem[3] = strlen(s);
int putchar(int ch)
{
- #define buffered_putch_bufsize 64
- static char buf[buffered_putch_bufsize];
+ static char buf[64];
static int buflen = 0;
if(ch != -1)
buf[buflen++] = ch;
- if(ch == -1 || buflen == buffered_putch_bufsize)
+ if(ch == -1 || buflen == sizeof(buf))
{
volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 4;
+ magic_mem[0] = SYS_write;
magic_mem[1] = 1;
magic_mem[2] = (long)buf;
magic_mem[3] = buflen;
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
#define rVlen a6
#define rStride a7
-#define rAI a8
-#define rBI a9
-#define rCI a10
+#define rAI t0
+#define rBI t1
+#define rCI t2
# WARNING: do not write to the s0,...,s9 registers without first saving them to
# the stack.
# Headers and Defines
#--------------------------------------------------------------------------
+#include "pcr.h"
+
# Here are some defines that make writing assembly code easier.
# I'm using the knowledge that rLda will be placed in register a0, rA will be
# address of VT function
#define rVTAddr v1
-#define rTemp0 a8
+#define rTemp0 t0
# desired app vector length (number of elements to vectorize)
-#define rNum a9
+#define rNum t1
-#define rATemp a10
-#define rBTemp a11
-#define rCTemp a12
-#define rI a13
+#define rATemp t2
+#define rBTemp t3
+#define rCTemp t4
+#define rI t5
#define rJ s1
#define rK s2
#define rLda4 a4
# turn on vector unit
- mfpcr a13,cr0
- ori a13,a13,4
- mtpcr x0,a13,cr0
+ setpcr status, SR_EV
blez rLda, cpdone # exit early if lda < 0
transpose:
# turn on vector unit
- mfpcr a13,cr0
- ori a13,a13,4
- mtpcr x0,a13,cr0
+ setpcr status, SR_EV
blez rLda, cpdone # exit early if lda < 0
printf( "*** FAILED *** (tohost = %d)\n", toHostValue );
exit(0);
#else
- asm( "mtpcr %0, cr30" : : "r" (toHostValue) );
+ asm( "mtpcr %0, tohost" : : "r" (toHostValue) );
while ( 1 ) { }
#endif
}
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
#define _ENV_PHYSICAL_SINGLE_CORE_H
+#include "../pcr.h"
+
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
#define RVTEST_RV64U \
+ .macro init; \
+ .endm
#define RVTEST_RV64UF \
- RVTEST_RV64U; \
- RVTEST_FP_ENABLE
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV64UV \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ RVTEST_VEC_ENABLE; \
+ .endm
#define RVTEST_RV32U \
- clearpcr cr0, 0x80
+ .macro init; \
+ RVTEST_32_ENABLE; \
+ .endm
+
+#define RVTEST_RV32UF \
+ .macro init; \
+ RVTEST_32_ENABLE; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV32UV \
+ .macro init; \
+ RVTEST_32_ENABLE; \
+ RVTEST_FP_ENABLE; \
+ RVTEST_VEC_ENABLE; \
+ .endm
#define RVTEST_RV64S \
+ .macro init; \
+ .endm
+
+#define RVTEST_32_ENABLE \
+ clearpcr status, SR_S64 \
#define RVTEST_FP_ENABLE \
- setpcr cr0, 2; \
- mfpcr a0, cr0; \
- and a0, a0, 2; \
+ setpcr status, SR_EF; \
+ mfpcr a0, status; \
+ and a0, a0, SR_EF; \
bnez a0, 2f; \
RVTEST_PASS; \
-2:mtfsr x0; \
+2:fssr x0; \
#define RVTEST_VEC_ENABLE \
- mfpcr a0, cr0; \
- ori a0, a0, 4; \
- mtpcr a0, cr0; \
- li a0, 0xff; \
- mtpcr a0, cr18; \
+ setpcr status, SR_EV; \
+ mfpcr a0, status; \
+ and a0, a0, SR_EV; \
+ bnez a0, 2f; \
+ RVTEST_PASS; \
+2: \
+
+#define RISCV_MULTICORE_DISABLE \
+ mfpcr a0, hartid; 1: bnez a0, 1b; \
+
+#define EXTRA_INIT
#define RVTEST_CODE_BEGIN \
.text; \
.align 4; \
.global _start; \
_start: \
- RVTEST_FP_ENABLE \
- RVTEST_VEC_ENABLE \
- mfpcr a0, cr10; 1: bnez a0, 1b; \
+ RISCV_MULTICORE_DISABLE; \
+ init; \
+ EXTRA_INIT; \
//-----------------------------------------------------------------------
// End Macro
#define RVTEST_PASS \
fence; \
li x1, 1; \
- mtpcr x1, cr30; \
+ mtpcr x1, tohost; \
1: b 1b; \
#define RVTEST_FAIL \
beqz x28, 1f; \
sll x28, x28, 1; \
or x28, x28, 1; \
- mtpcr x28, cr30; \
+ mtpcr x28, tohost; \
1: b 1b; \
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
-#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_BEGIN EXTRA_DATA
#define RVTEST_DATA_END
+#define EXTRA_DATA
+
//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
--- /dev/null
+// See LICENSE for license details.
+
+#ifndef _RISCV_PCR_H
+#define _RISCV_PCR_H
+
+#define SR_S 0x00000001
+#define SR_PS 0x00000002
+#define SR_EI 0x00000004
+#define SR_PEI 0x00000008
+#define SR_EF 0x00000010
+#define SR_U64 0x00000020
+#define SR_S64 0x00000040
+#define SR_VM 0x00000080
+#define SR_EV 0x00000100
+#define SR_IM 0x00FF0000
+#define SR_IP 0xFF000000
+#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
+#define SR_IM_SHIFT 16
+#define SR_IP_SHIFT 24
+
+#define PCR_SUP0 0
+#define PCR_SUP1 1
+#define PCR_EPC 2
+#define PCR_BADVADDR 3
+#define PCR_PTBR 4
+#define PCR_ASID 5
+#define PCR_COUNT 6
+#define PCR_COMPARE 7
+#define PCR_EVEC 8
+#define PCR_CAUSE 9
+#define PCR_SR 10
+#define PCR_HARTID 11
+#define PCR_IMPL 12
+#define PCR_FATC 13
+#define PCR_SEND_IPI 14
+#define PCR_CLR_IPI 15
+#define PCR_VECBANK 18
+#define PCR_VECCFG 19
+#define PCR_RESET 29
+#define PCR_TOHOST 30
+#define PCR_FROMHOST 31
+
+#define IRQ_COP 2
+#define IRQ_IPI 5
+#define IRQ_HOST 6
+#define IRQ_TIMER 7
+
+#define IMPL_SPIKE 1
+#define IMPL_ROCKET 2
+
+#define CAUSE_MISALIGNED_FETCH 0
+#define CAUSE_FAULT_FETCH 1
+#define CAUSE_ILLEGAL_INSTRUCTION 2
+#define CAUSE_PRIVILEGED_INSTRUCTION 3
+#define CAUSE_FP_DISABLED 4
+#define CAUSE_SYSCALL 6
+#define CAUSE_BREAKPOINT 7
+#define CAUSE_MISALIGNED_LOAD 8
+#define CAUSE_MISALIGNED_STORE 9
+#define CAUSE_FAULT_LOAD 10
+#define CAUSE_FAULT_STORE 11
+#define CAUSE_VECTOR_DISABLED 12
+#define CAUSE_VECTOR_BANK 13
+
+#define CAUSE_VECTOR_MISALIGNED_FETCH 24
+#define CAUSE_VECTOR_FAULT_FETCH 25
+#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
+#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
+#define CAUSE_VECTOR_MISALIGNED_LOAD 28
+#define CAUSE_VECTOR_MISALIGNED_STORE 29
+#define CAUSE_VECTOR_FAULT_LOAD 30
+#define CAUSE_VECTOR_FAULT_STORE 31
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Entry is a page Table descriptor
+#define PTE_T 0x002 // Entry is a page Table, not a terminal node
+#define PTE_G 0x004 // Global
+#define PTE_UR 0x008 // User Write permission
+#define PTE_UW 0x010 // User Read permission
+#define PTE_UX 0x020 // User eXecute permission
+#define PTE_SR 0x040 // Supervisor Read permission
+#define PTE_SW 0x080 // Supervisor Write permission
+#define PTE_SX 0x100 // Supervisor eXecute permission
+#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define RISCV_PGLEVELS 3
+# define RISCV_PGSHIFT 13
+#else
+# define RISCV_PGLEVELS 2
+# define RISCV_PGSHIFT 12
+#endif
+#define RISCV_PGLEVEL_BITS 10
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
+ asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
+ __tmp2; })
+
+#define mfpcr(reg) ({ long __tmp; \
+ asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
+ __tmp; })
+
+#define setpcr(reg,val) ({ long __tmp; \
+ asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+ __tmp; })
+
+#define clearpcr(reg,val) ({ long __tmp; \
+ asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+ __tmp; })
+
+#define rdcycle() ({ unsigned long __tmp; \
+ asm volatile ("rdcycle %0" : "=r"(__tmp)); \
+ __tmp; })
+
+#endif
+
+#endif
+
+#endif
#ifndef _ENV_PHYSICAL_MULTI_CORE_H
-#define _ENV_PHYSICAL_MULTI_CORE_H
+#define _ENV_PHYSICAL_MULTI_CORE_HA
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
+#include "../p/riscv_test.h"
-#define RVTEST_RV64U \
-
-#define RVTEST_RV64UF \
- RVTEST_RV64U; \
- RVTEST_FP_ENABLE
-
-#define RVTEST_RV64S \
-
-#define RVTEST_FP_ENABLE \
- setpcr cr0, 2; \
- mfpcr a0, cr0; \
- and a0, a0, 2; \
- bnez a0, 2f; \
- RVTEST_PASS; \
-2:mtfsr x0; \
-
-#define RVTEST_VEC_ENABLE \
- mfpcr a0, cr0; \
- ori a0, a0, 4; \
- mtpcr a0, cr0; \
- li a0, 0xff; \
- mtpcr a0, cr18; \
-
-#define RVTEST_CODE_BEGIN \
- .text; \
- .align 4; \
- .global _start; \
-_start: \
- RVTEST_FP_ENABLE \
- RVTEST_VEC_ENABLE \
-
-//-----------------------------------------------------------------------
-// End Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_CODE_END \
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_FAIL \
- fence; \
- beqz x28, 1f; \
- sll x28, x28, 1; \
- or x28, x28, 1; \
- mtpcr x28, cr30; \
-1: b 1b; \
-
-#define RVTEST_PASS \
- fence; \
- li x1, 1; \
- mtpcr x1, cr30; \
-1: b 1b; \
-
-//-----------------------------------------------------------------------
-// Data Section Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_DATA_BEGIN
-#define RVTEST_DATA_END
-
-//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
-//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+#undef RISCV_MULTICORE_DISABLE
+#define RISCV_MULTICORE_DISABLE
#endif
#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
-#include "pcr.h"
+#include "../p/riscv_test.h"
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_RV64U \
-
-#define RVTEST_RV64UF \
- RVTEST_RV64U; \
- RVTEST_FP_ENABLE
-
-#define RVTEST_FP_ENABLE \
- setpcr cr0, 2; \
- mfpcr a0, cr0; \
- and a0, a0, 2; \
- bnez a0, 2f; \
- RVTEST_PASS; \
-2:mtfsr x0; \
-
-#define RVTEST_VEC_ENABLE \
- mfpcr a0, cr0; \
- ori a0, a0, 4; \
- mtpcr a0, cr0; \
- li a0, 0xff; \
- mtpcr a0, cr18; \
-
-#define RVTEST_CODE_BEGIN \
- .text; \
- .align 4; \
- .global _start; \
-_start: \
- RVTEST_FP_ENABLE \
- RVTEST_VEC_ENABLE \
- mfpcr a0, cr10; 1: bnez a0, 1b; \
- ENABLE_TIMER_INTERRUPT \
-
-//-----------------------------------------------------------------------
-// End Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_CODE_END \
- XCPT_HANDLER \
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_PASS \
- fence; \
- li x1, 1; \
- mtpcr x1, cr30; \
-1: b 1b; \
-
-#define RVTEST_FAIL \
- fence; \
- beqz x28, 1f; \
- sll x28, x28, 1; \
- or x28, x28, 1; \
- mtpcr x28, cr30; \
-1: b 1b; \
+#undef EXTRA_INIT
+#define EXTRA_INIT \
+ ENABLE_TIMER_INTERRUPT; \
+ b 6f; \
+ XCPT_HANDLER; \
+6:
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
-#define RVTEST_DATA_BEGIN \
- .align 3; \
+#undef EXTRA_DATA
+#define EXTRA_DATA \
+ .align 3; \
regspill: \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
-#define RVTEST_DATA_END
-
-//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
-//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
-
//-----------------------------------------------------------------------
// Misc
//-----------------------------------------------------------------------
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
- mfpcr x3,ASM_CR(PCR_K0)
+ mfpcr x3,sup0
STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0
- mfpcr x3,ASM_CR(PCR_K1)
+ mfpcr x3,sup1
STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1
# get sr, epc, badvaddr, cause
- mfpcr x3,ASM_CR(PCR_SR) # sr
+ mfpcr x3,status # sr
STORE x3,32*REGBYTES(x2)
- mfpcr x4,ASM_CR(PCR_EPC) # epc
+ mfpcr x4,epc # epc
STORE x4,33*REGBYTES(x2)
- mfpcr x3,ASM_CR(PCR_BADVADDR) # badvaddr
+ mfpcr x3,badvaddr # badvaddr
STORE x3,34*REGBYTES(x2)
- mfpcr x3,ASM_CR(PCR_CAUSE) # cause
+ mfpcr x3,cause # cause
STORE x3,35*REGBYTES(x2)
# get faulting insn, if it wasn't a fetch-related trap
sh x4,2+36*REGBYTES(x2)
1:
- mfpcr x3,ASM_CR(PCR_VECBANK) # vecbank
- STORE x3,37*REGBYTES(x2)
- mfpcr x3,ASM_CR(PCR_VECCFG) # veccfg
- STORE x3,38*REGBYTES(x2)
+ #mfpcr x3,ASM_CR(PCR_VECBANK) # vecbank
+ #STORE x3,37*REGBYTES(x2)
+ #mfpcr x3,ASM_CR(PCR_VECCFG) # veccfg
+ #STORE x3,38*REGBYTES(x2)
ret
pop_tf: # write the trap frame onto the stack
# restore gprs
LOAD a1,32*REGBYTES(a0) # restore sr (should disable interrupts)
- mtpcr a1,ASM_CR(PCR_SR)
+ mtpcr a1,status
LOAD x1,1*REGBYTES(a0)
- mtpcr x1,ASM_CR(PCR_K0)
+ mtpcr x1,sup0
LOAD x1,2*REGBYTES(a0)
- mtpcr x1,ASM_CR(PCR_K1)
+ mtpcr x1,sup1
move x1,a0
LOAD x3,3*REGBYTES(x1)
LOAD x4,4*REGBYTES(x1)
# gtfo!
LOAD x2,33*REGBYTES(x1)
- mtpcr x2,ASM_CR(PCR_EPC)
- mfpcr x1,ASM_CR(PCR_K0)
- mfpcr x2,ASM_CR(PCR_K1)
+ mtpcr x2,epc
+ mfpcr x1,sup0
+ mfpcr x2,sup1
eret
.global trap_entry
trap_entry:
- mtpcr ra,ASM_CR(PCR_K0)
- mtpcr x2,ASM_CR(PCR_K1)
+ mtpcr ra,sup0
+ mtpcr x2,sup1
# coming from kernel?
- mfpcr ra,ASM_CR(PCR_SR)
+ mfpcr ra,status
and ra,ra,SR_PS
bnez ra, 1f
la x2,stack_top+MAX_TEST_PAGES*PGSIZE-SIZEOF_TRAPFRAME_T
jal save_tf
move sp,x2
- setpcr ASM_CR(PCR_SR), SR_ET
+ setpcr status, SR_EI
move a0,x2
- mfpcr ra,ASM_CR(PCR_SR)
+ mfpcr ra,status
and ra,ra,SR_EV
beqz ra, 2f
addi x2,x2,39*REGBYTES
1:add x2, sp, -SIZEOF_TRAPFRAME_T
jal save_tf
move sp,x2
- setpcr ASM_CR(PCR_SR), SR_ET
+ setpcr status, SR_EI
move a0,x2
jal handle_trap
+++ /dev/null
-#ifndef _RISCV_PCR_H
-#define _RISCV_PCR_H
-
-#define SR_ET 0x00000001
-#define SR_EF 0x00000002
-#define SR_EV 0x00000004
-#define SR_EC 0x00000008
-#define SR_PS 0x00000010
-#define SR_S 0x00000020
-#define SR_U64 0x00000040
-#define SR_S64 0x00000080
-#define SR_VM 0x00000100
-#define SR_IM 0x00FF0000
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
-#define SR_IM_SHIFT 16
-
-#define PCR_SR 0
-#define PCR_EPC 1
-#define PCR_BADVADDR 2
-#define PCR_EVEC 3
-#define PCR_COUNT 4
-#define PCR_COMPARE 5
-#define PCR_CAUSE 6
-#define PCR_PTBR 7
-#define PCR_SEND_IPI 8
-#define PCR_CLR_IPI 9
-#define PCR_COREID 10
-#define PCR_IMPL 11
-#define PCR_K0 12
-#define PCR_K1 13
-#define PCR_VECBANK 18
-#define PCR_VECCFG 19
-#define PCR_RESET 29
-#define PCR_TOHOST 30
-#define PCR_FROMHOST 31
-
-#define IMPL_ISASIM 1
-#define IMPL_ROCKET 2
-
-#define IRQ_IPI 5
-#define IRQ_TIMER 7
-
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_VECTOR_DISABLED 12
-#define CAUSE_VECTOR_BANK 13
-
-#define CAUSE_VECTOR_MISALIGNED_FETCH 24
-#define CAUSE_VECTOR_FAULT_FETCH 25
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
-#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
-#define CAUSE_VECTOR_MISALIGNED_LOAD 28
-#define CAUSE_VECTOR_MISALIGNED_STORE 29
-#define CAUSE_VECTOR_FAULT_LOAD 30
-#define CAUSE_VECTOR_FAULT_STORE 31
-
-#ifdef __riscv
-
-#define ASM_CR(r) _ASM_CR(r)
-#define _ASM_CR(r) cr##r
-
-#ifndef __ASSEMBLER__
-
-#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
- asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
- __tmp2; })
-
-#define mfpcr(reg) ({ long __tmp; \
- asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
- __tmp; })
-
-#define setpcr(reg,val) ({ long __tmp; \
- asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
- __tmp; })
-
-#define clearpcr(reg,val) ({ long __tmp; \
- asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
- __tmp; })
-
-#endif
-
-#endif
-
-#endif
//-----------------------------------------------------------------------
#define RVTEST_RV64U \
- .text; \
-init: \
- ret
+ .macro init; \
+ .endm
#define RVTEST_RV64UF \
- .text; \
-init: \
- mtfsr x0; \
- ret
-
-#define RVTEST_RV64S \
+ .macro init; \
+ fssr x0; \
+ .endm
#define RVTEST_VEC_ENABLE \
- mfpcr t0, cr0; \
- ori t0, t0, 4; \
- mtpcr t0, cr0; \
- li t0, 0xff; \
- mtpcr t0, cr11; \
#define RVTEST_CODE_BEGIN \
.text; \
.align 13; \
.global userstart; \
userstart: \
- jal init
+ init
//-----------------------------------------------------------------------
// End Macro
// Supervisor mode definitions and macros
//-----------------------------------------------------------------------
-#include "pcr.h"
+#include "../pcr.h"
#define vvcfg(nxregs, nfregs) ({ \
asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
if (*RELOC(&freelist_head) == *RELOC(&freelist_tail))
*RELOC(&freelist_tail) = 0;
- *RELOC(&l3pt[addr/PGSIZE]) = node->addr | 0x3F2;
- mtpcr(PCR_PTBR, l1pt);
+ *RELOC(&l3pt[addr/PGSIZE]) = node->addr | PTE_UW | PTE_UR | PTE_UX | PTE_SW | PTE_SR | PTE_SX | PTE_V;
+ mtpcr(PCR_FATC, 0);
assert(RELOC(&user_mapping[addr/PGSIZE])->addr == 0);
*RELOC(&user_mapping[addr/PGSIZE]) = *node;
handle_fault(tf->epc);
else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
{
- int mtfsr;
- asm ("la %0, 1f; lw %0, 0(%0); b 2f; 1: mtfsr x0; 2:" : "=r"(mtfsr));
+ int fssr;
+ asm ("la %0, 1f; lw %0, 0(%0); b 2f; 1: fssr x0; 2:" : "=r"(fssr));
- if (tf->insn == mtfsr)
+ if (tf->insn == fssr)
terminate(1); // FP test on non-FP hardware. "succeed."
else if ((tf->insn & 0xF83FFFFF) == 0x37B)
emulate_vxcptsave(tf);
void vm_boot(long test_addr, long seed)
{
- while (mfpcr(PCR_COREID) > 0); // only core 0 proceeds
+ while (mfpcr(PCR_HARTID) > 0); // only core 0 proceeds
assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t));
freelist_nodes[MAX_TEST_PAGES-1].next = 0;
assert(MAX_TEST_PAGES*2 < PTES_PER_PT);
- l1pt[0] = (pte_t)l2pt | 1;
- l2pt[0] = (pte_t)l3pt | 1;
+ l1pt[0] = (pte_t)l2pt | PTE_V | PTE_T;
+ l2pt[0] = (pte_t)l3pt | PTE_V | PTE_T;
for (long i = 0; i < MAX_TEST_PAGES; i++)
- l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | 0x382;
+ l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | PTE_SW | PTE_SR | PTE_SX | PTE_V;
mtpcr(PCR_PTBR, l1pt);
mtpcr(PCR_SR, mfpcr(PCR_SR) | SR_VM | SR_EF);
asm volatile ("add sp, sp, %1; rdpc %0; addi %0, %0, 16; add %0, %0, %1; jr %0" : "=&r"(tmp) : "r"(adjustment));
memset(RELOC(&l3pt[0]), 0, MAX_TEST_PAGES*sizeof(pte_t));
- mtpcr(PCR_PTBR, l1pt);
+ mtpcr(PCR_FATC, 0);
trapframe_t tf;
memset(&tf, 0, sizeof(tf));
include $(isa_src_dir)/rv64ui/Makefrag
include $(isa_src_dir)/rv64uf/Makefrag
-include $(isa_src_dir)/rv64uv/Makefrag
+#include $(isa_src_dir)/rv64uv/Makefrag
include $(isa_src_dir)/rv64si/Makefrag
include $(isa_src_dir)/rv64sv/Makefrag
include $(isa_src_dir)/rv32ui/Makefrag
#--------------------------------------------------------------------
RISCV_GCC = riscv-gcc
-RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
RISCV_OBJDUMP = riscv-objdump --disassemble-all --section=.text --section=.data --section=.bss
RISCV_SIM = spike
$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
tests += $$($(1)_v_tests)
-$$($(1)_p_vec_tests): $(1)-p-vec-%: $(1)/%.S
- $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/p -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
-tests += $$($(1)_p_vec_tests)
-
-$$($(1)_pt_vec_tests): $(1)-pt-vec-%: $(1)/%.S
- $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
-tests += $$($(1)_pt_vec_tests)
-
-$$($(1)_v_vec_tests): $(1)-v-vec-%: $(1)/%.S
- $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
-tests += $$($(1)_v_vec_tests)
+#$$($(1)_p_vec_tests): $(1)-p-vec-%: $(1)/%.S
+# $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/p -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
+#tests += $$($(1)_p_vec_tests)
+#
+#$$($(1)_pt_vec_tests): $(1)-pt-vec-%: $(1)/%.S
+# $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
+#tests += $$($(1)_pt_vec_tests)
+#
+#$$($(1)_v_vec_tests): $(1)-v-vec-%: $(1)/%.S
+# $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
+#tests += $$($(1)_v_vec_tests)
endef
#define TEST_FCVT_S_D( testnum, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
- fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d a0, f3)
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
#define TEST_FCVT_D_S( testnum, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
- fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s a0, f3)
+ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
- inst f3, f0; mftx.s a0, f3)
+ inst f3, f0; fmv.x.s a0, f3)
#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
- inst f3, f0; mftx.d a0, f3)
+ inst f3, f0; fmv.x.d a0, f3)
#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.s a0, f3)
+ inst f3, f0, f1; fmv.x.s a0, f3)
#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.d a0, f3)
+ inst f3, f0, f1; fmv.x.d a0, f3)
#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.s a0, f3)
+ inst f3, f0, f1, f2; fmv.x.s a0, f3)
#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.d a0, f3)
+ inst f3, f0, f1, f2; fmv.x.d a0, f3)
#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
TEST_FP_OP_S_INTERNAL( testnum, word result, val1, 0.0, 0.0, \
lw a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
- mftx.s a0, f0; \
+ fmv.x.s a0, f0; \
bne a0, a3, fail; \
b 1f; \
.align 2; \
ld a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
- mftx.d a0, f0; \
+ fmv.x.d a0, f0; \
bne a0, a3, fail; \
b 1f; \
.align 3; \
#define TEST_FCVT_S_D( testnum, result, val1 ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
- fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d x1, f3)
+ fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d x1, f3)
#define TEST_FCVT_D_S( testnum, result, val1 ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
- fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s x1, f3)
+ fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.s x1, f3)
+ inst f3, f0, f1; fmv.x.s x1, f3)
#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
- inst f3, f0, f1; mftx.d x1, f3)
+ inst f3, f0, f1; fmv.x.d x1, f3)
#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.s x1, f3)
+ inst f3, f0, f1, f2; fmv.x.s x1, f3)
#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
- inst f3, f0, f1, f2; mftx.d x1, f3)
+ inst f3, f0, f1, f2; fmv.x.d x1, f3)
#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
vtcode ## testnum : \
li x1, val1; \
inst f0, x1; \
- mftx.s x1, f0; \
+ fmv.x.s x1, f0; \
stop; \
.align 2; \
test_ ## testnum ## _data: \
vtcode ## testnum : \
li x1, val1; \
inst f0, x1; \
- mftx.d x1, f0; \
+ fmv.x.d x1, f0; \
stop; \
.align 3; \
test_ ## testnum ## _data: \
# Basic tests
#-------------------------------------------------------------
- TEST_CASE( 2, x1, 0x0, mfpcr x1, cr12 );
+ TEST_CASE( 2, x1, 0x0, mfpcr x1, hartid );
TEST_PASSFAIL
# clear pending IPIs then enable interrupts
la a0, handler
- mtpcr a0, cr3
- mtpcr x0, cr9
- mfpcr a0, cr0
- li a1, 0x00ff0001
+ mtpcr a0, evec
+ mtpcr x0, clear_ipi
+ mfpcr a0, status
+ li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
or a0, a0, a1
- mtpcr a0, cr0
+ mtpcr a0, status
# wait for all cores to boot
la a0, coreid
blt a1, a3, 1b
# IPI dominoes
- mfpcr a0, cr10
+ mfpcr a0, hartid
1: bnez a0, 1b
add a0, a0, 1
rem a0, a0, a3
- mtpcr a0, cr8
+ mtpcr a0, send_ipi
1: b 1b
handler:
- mfpcr a0, cr10
+ mfpcr a0, hartid
bnez a0, 2f
RVTEST_PASS
2: add a0, a0, 1
rem a0, a0, a3
- mtpcr a0, cr8
+ mtpcr a0, send_ipi
1: b 1b
RVTEST_CODE_END
rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
+spike_tests += $(rv64uf_p_tests) #$(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
# move.S
#-----------------------------------------------------------------------------
#
-# This test verifies that mxtf.[s,d], mftx.[s,d], mtfsr, mffsr,
+# This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr,
# and fsgnj[x|n].[s|d] work properly.
#
RVTEST_CODE_BEGIN
li a0, 1
-mtfsr a0
+fssr a0
- TEST_CASE(2, a1, 1, li a0, 0x1234; mtfsr a1, a0)
- TEST_CASE(3, a0, 0x34, mffsr a0)
- TEST_CASE(4, a0, 0x34, mffsr a0)
+ TEST_CASE(2, a1, 1, li a0, 0x1234; fssr a1, a0)
+ TEST_CASE(3, a0, 0x34, frsr a0)
+ TEST_CASE(4, a0, 0x34, frsr a0)
- TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; mxtf.s f0, a1; mftx.s a0, f0)
- TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; mxtf.d f1, a1; mftx.d a0, f1)
+ TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fmv.x.s a0, f0)
+ TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1)
- TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; mxtf.s f0, a1; fsgnj.s f1, f0, f0; mftx.s a0, f1)
- TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; mxtf.s f0, a1; fsgnjx.s f1, f0, f0; mftx.s a0, f1)
- TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; mxtf.s f0, a1; fsgnjn.s f1, f0, f0; mftx.s a0, f1)
- TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; mxtf.d f1, a1; mxtf.d f2, a2; fsgnj.d f0, f1, f2; mftx.d a0, f0)
+ TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1)
+ TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1)
+ TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1)
+ TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0)
TEST_PASSFAIL
li x1, 0x3F800000
#define TEST(nops, errcode) \
- mxtf.d f4, x0 ;\
- mxtf.s f3, x0 ;\
- mxtf.d f2, x2 ;\
- mxtf.s f1, x1 ;\
+ fmv.d.x f4, x0 ;\
+ fmv.s.x f3, x0 ;\
+ fmv.d.x f2, x2 ;\
+ fmv.s.x f1, x1 ;\
b 1f ;\
.align 5 ;\
1:fmul.d f4, f2, f2 ;\
nops ;\
fsgnj.s f3, f1, f1 ;\
- mftx.d x4, f4 ;\
- mftx.s x3, f3 ;\
+ fmv.x.d x4, f4 ;\
+ fmv.x.s x3, f3 ;\
beq x1, x3, 2f ;\
RVTEST_FAIL ;\
2:beq x2, x4, 2f ;\
RVTEST_FAIL; \
-2:mxtf.d f2, zero ;\
- mxtf.s f1, zero ;\
+2:fmv.d.x f2, zero ;\
+ fmv.s.x f1, zero ;\
TEST(;,2)
TEST(nop,4)
rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) #$(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
la a4,src
fld f0,0(a4)
fld f1,8(a4)
- mftx.d s0,f0
- mftx.d s1,f1
+ fmv.x.d s0,f0
+ fmv.x.d s1,f1
vmsv vx1,s0
vmsv vx2,s1
lui a0,%hi(vtcode)
bne a7,a6,wait
fadd.d f0,f0,f1
- mftx.d s2,f0
+ fmv.x.d s2,f0
la a5,dest
vfsd vf0,a5
j pass
vtcode:
- mxtf.d f0,x1
- mxtf.d f1,x2
+ fmv.d.x f0,x1
+ fmv.d.x f1,x2
fadd.d f0,f0,f1
stop
slti x2,x1,10
li x1,-1
li x3,0
- mxtf.d f0,x3
- mxtf.d f1,x1
+ fmv.d.x f0,x3
+ fmv.d.x f1,x1
fmovn f0,x2,f1
stop
slti x2,x1,10
li x1,-1
li x3,0
- mxtf.d f0,x3
- mxtf.d f1,x1
+ fmv.d.x f0,x3
+ fmv.d.x f1,x1
fmovz f0,x2,f1
stop
vtcode:
utidx x1
addi x1,x1,1
- mxtf.d f0,x1
+ fmv.d.x f0,x1
stop
TEST_PASSFAIL
--- /dev/null
+*.riscv
+*.host
+*.o
+*.dump
+*.out
+*.hex
default: all
bmarkdir = .
+common = ../benchmarks/common
instname = riscv-bmarks-mt
instbasedir = $(UCB_VLSI_HOME)/install
RISCV_GCC = riscv-gcc
RISCV_GCC_OPTS = -std=gnu99 -T common/test.ld -O3 -nostdlib -nostartfiles -funroll-all-loops
-RISCV_LINK = riscv-gcc -T $(bmarkdir)/common/test.ld
-RISCV_LINK_MT = riscv-gcc -T $(bmarkdir)/common/test-mt.ld
+RISCV_LINK = riscv-gcc -T $(common)/test.ld
+RISCV_LINK_MT = riscv-gcc -T $(common)/test-mt.ld
RISCV_LINK_OPTS = -lc
-RISCV_LINK_SYSCALL = $(bmarkdir)/common/syscalls.c -lc
+RISCV_LINK_SYSCALL = $(common)/syscalls.c -lc
RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
RISCV_SIM = spike -p2
VPATH += $(addprefix $(bmarkdir)/, $(bmarks))
-VPATH += $(bmarkdir)/common
+VPATH += $(common)
-incs += -I. -I./common $(addprefix -I$(bmarkdir)/, $(bmarks))
+incs += -I. -I$(common) $(addprefix -I$(bmarkdir)/, $(bmarks))
objs :=
#include $(patsubst %, $(bmarkdir)/%/bmark.mk, $(bmarks))
+++ /dev/null
- .data
- .globl _heapend
- .globl environ
-_heapend:
- .word 0
-environ:
- .word 0
-
- .text
- .globl _start
-
-_start:
- li x1, 0
- li x2, 0
- li x3, 0
- li x4, 0
- li x5, 0
- li x6, 0
- li x7, 0
- li x8, 0
- li x9, 0
- li x10,0
- li x11,0
- li x12,0
- li x13,0
- li x14,0
- li x15,0
- li x16,0
- li x17,0
- li x18,0
- li x19,0
- li x20,0
- li x21,0
- li x22,0
- li x23,0
- li x24,0
- li x25,0
- li x26,0
- li x27,0
- li x28,0
- li x29,0
- li x30,0
- li x31,0
-
- # enable fp
- mfpcr x1,cr0
- ori x1,x1,0x2
- mtpcr x1,cr0
-
- # enable vec
- mfpcr x1,cr0
- ori x1,x1,0x4
- mtpcr x1,cr0
-
- ## if that didn't stick, we don't have an FPU, so don't initialize it
- mfpcr x1,cr0
- andi x1,x1,0x2
- beqz x1,1f
-
- mtfsr x0
- mxtf.s f0, x0
- mxtf.s f1, x0
- mxtf.s f2, x0
- mxtf.s f3, x0
- mxtf.s f4, x0
- mxtf.s f5, x0
- mxtf.s f6, x0
- mxtf.s f7, x0
- mxtf.s f8, x0
- mxtf.s f9, x0
- mxtf.s f10,x0
- mxtf.s f11,x0
- mxtf.s f12,x0
- mxtf.s f13,x0
- mxtf.s f14,x0
- mxtf.s f15,x0
- mxtf.s f16,x0
- mxtf.s f17,x0
- mxtf.s f18,x0
- mxtf.s f19,x0
- mxtf.s f20,x0
- mxtf.s f21,x0
- mxtf.s f22,x0
- mxtf.s f23,x0
- mxtf.s f24,x0
- mxtf.s f25,x0
- mxtf.s f26,x0
- mxtf.s f27,x0
- mxtf.s f28,x0
- mxtf.s f29,x0
- mxtf.s f30,x0
- mxtf.s f31,x0
-1:
-
- # get core id and number of cores
- mfpcr a0,cr10
- lw a1, 4(zero)
-
- slli a2, a0, 13
- la sp, stacktop
- sub sp, sp, a2
-
- la tp, tlstop
- sub tp, tp, a2
-
- jal thread_entry
-
- .bss
- .globl stacktop
- .globl tlstop
-
- .align 4
- .skip 32768
-stacktop:
- .skip 65536
-tlstop:
+++ /dev/null
- .data
- .globl _heapend
- .globl environ
-_heapend:
- .word 0
-environ:
- .word 0
-
- .text
- .globl _start
-
-_start:
- li x1, 0
- li x2, 0
- li x3, 0
- li x4, 0
- li x5, 0
- li x6, 0
- li x7, 0
- li x8, 0
- li x9, 0
- li x10,0
- li x11,0
- li x12,0
- li x13,0
- li x14,0
- li x15,0
- li x16,0
- li x17,0
- li x18,0
- li x19,0
- li x20,0
- li x21,0
- li x22,0
- li x23,0
- li x24,0
- li x25,0
- li x26,0
- li x27,0
- li x28,0
- li x29,0
- li x30,0
- li x31,0
-
- # enable fp
- mfpcr x1,cr0
- ori x1,x1,0x2
- mtpcr x1,cr0
-
- # enable vec
- mfpcr x1,cr0
- ori x1,x1,0x4
- mtpcr x1,cr0
-
- ## if that didn't stick, we don't have an FPU, so don't initialize it
- mfpcr x1,cr0
- andi x1,x1,0x2
- beqz x1,1f
-
- mtfsr x0
- mxtf.s f0, x0
- mxtf.s f1, x0
- mxtf.s f2, x0
- mxtf.s f3, x0
- mxtf.s f4, x0
- mxtf.s f5, x0
- mxtf.s f6, x0
- mxtf.s f7, x0
- mxtf.s f8, x0
- mxtf.s f9, x0
- mxtf.s f10,x0
- mxtf.s f11,x0
- mxtf.s f12,x0
- mxtf.s f13,x0
- mxtf.s f14,x0
- mxtf.s f15,x0
- mxtf.s f16,x0
- mxtf.s f17,x0
- mxtf.s f18,x0
- mxtf.s f19,x0
- mxtf.s f20,x0
- mxtf.s f21,x0
- mxtf.s f22,x0
- mxtf.s f23,x0
- mxtf.s f24,x0
- mxtf.s f25,x0
- mxtf.s f26,x0
- mxtf.s f27,x0
- mxtf.s f28,x0
- mxtf.s f29,x0
- mxtf.s f30,x0
- mxtf.s f31,x0
-1:
-
- # only allow core 0 to proceed
-1:mfpcr a0, cr10
- bnez a0, 1b
-
- la sp,stacktop
- jal main
-1:b 1b
-
- .bss
- .globl stacktop
-
- .align 4
- .skip 131072
-stacktop:
+++ /dev/null
-#ifndef _RISCV_PCR_H
-#define _RISCV_PCR_H
-
-#define SR_ET 0x00000001
-#define SR_EF 0x00000002
-#define SR_EV 0x00000004
-#define SR_EC 0x00000008
-#define SR_PS 0x00000010
-#define SR_S 0x00000020
-#define SR_U64 0x00000040
-#define SR_S64 0x00000080
-#define SR_VM 0x00000100
-#define SR_IM 0x00FF0000
-#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
-#define SR_IM_SHIFT 16
-
-#define PCR_SR 0
-#define PCR_EPC 1
-#define PCR_BADVADDR 2
-#define PCR_EVEC 3
-#define PCR_COUNT 4
-#define PCR_COMPARE 5
-#define PCR_CAUSE 6
-#define PCR_PTBR 7
-#define PCR_SEND_IPI 8
-#define PCR_CLR_IPI 9
-#define PCR_COREID 10
-#define PCR_IMPL 11
-#define PCR_K0 12
-#define PCR_K1 13
-#define PCR_VECBANK 18
-#define PCR_VECCFG 19
-#define PCR_RESET 29
-#define PCR_TOHOST 30
-#define PCR_FROMHOST 31
-
-#define IRQ_IPI 5
-#define IRQ_TIMER 7
-
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_VECTOR_DISABLED 12
-#define CAUSE_VECTOR_BANK 13
-
-#define CAUSE_VECTOR_MISALIGNED_FETCH 24
-#define CAUSE_VECTOR_FAULT_FETCH 25
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
-#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
-#define CAUSE_VECTOR_MISALIGNED_LOAD 28
-#define CAUSE_VECTOR_MISALIGNED_STORE 29
-#define CAUSE_VECTOR_FAULT_LOAD 30
-#define CAUSE_VECTOR_FAULT_STORE 31
-
-#ifdef __riscv
-
-#define ASM_CR(r) _ASM_CR(r)
-#define _ASM_CR(r) cr##r
-
-#ifndef __ASSEMBLER__
-
-#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
- asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
- __tmp2; })
-
-#define mfpcr(reg) ({ long __tmp; \
- asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
- __tmp; })
-
-#define setpcr(reg,val) ({ long __tmp; \
- asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
- __tmp; })
-
-#define clearpcr(reg,val) ({ long __tmp; \
- asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
- __tmp; })
-
-#endif
-
-#endif
-
-#endif
+++ /dev/null
- .file 1 "syscalls.c"
- .section .mdebug.abi64
- .previous
- .section .rodata.str1.8,"aMS",@progbits,1
- .align 3
-$LC0:
- .ascii "0123456789abcdef\000"
- .text
- .align 2
- .ent printnum
- .type printnum, @function
-printnum:
- .frame x30,64,x1 # vars= 0, regs= 7/0, args= 0
- .mask 0x03f00002,-8
- .fmask 0x00000000,0
- add x30,x30,-64
- sd x22,32(x30)
- sll x22,x7,32
- srl x22,x22,32
- sd x24,48(x30)
- sd x23,40(x30)
- sd x21,24(x30)
- sd x20,16(x30)
- sd x25,56(x30)
- sd x1,8(x30)
- move x23,x6
- move x20,x4
- move x21,x5
- move x24,x9
- bleu x22,x6,$L2
- addw x8,x8,-1
- move x25,x8
- ble x8,x0,$L4
-$L6:
- addw x25,x25,-1
- move x4,x24
- move x5,x21
- jalr x20
- bne x25,x0,$L6
-$L4:
- lui x2,%hi($LC0)
- add x2,x2,%lo($LC0)
- remu x22,x23,x22
- add x22,x22,x2
- lb x4,0(x22)
- move x5,x21
- move x19,x20
- ld x25,56(x30)
- ld x24,48(x30)
- ld x23,40(x30)
- ld x22,32(x30)
- ld x21,24(x30)
- ld x20,16(x30)
- ld x1,8(x30)
- add x30,x30,64
- jr x19
-$L2:
- addw x8,x8,-1
- divu x6,x6,x22
- jal printnum
- j $L4
- .end printnum
- .size printnum, .-printnum
- .align 2
- .ent getuint
- .type getuint, @function
-getuint:
- .frame x30,0,x1 # vars= 0, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- slt x2,x5,2
- bne x2,x0,$L10
-$L13:
- ld x2,0(x4)
- add x3,x2,8
- sd x3,0(x4)
- ld x2,0(x2)
- ret
-$L10:
- bne x5,x0,$L13
- ld x3,0(x4)
- lwu x2,0(x3)
- add x3,x3,8
- sd x3,0(x4)
- ret
- .end getuint
- .size getuint, .-getuint
- .align 2
- .globl putchar
- .ent putchar
- .type putchar, @function
-putchar:
- .frame x30,64,x1 # vars= 64, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- li x2,-1 # 0xffffffffffffffff
- add x30,x30,-64
- lui x3,%hi(buflen.1596)
- beq x4,x2,$L21
- lw x5,%lo(buflen.1596)(x3)
- lui x2,%hi(buf.1595)
- add x2,x2,%lo(buf.1595)
- add x6,x2,x5
- sb x4,0(x6)
- addw x5,x5,1
- li x4,64 # 0x40
- sw x5,%lo(buflen.1596)(x3)
- beq x5,x4,$L15
- move x2,x0
- add x30,x30,64
- j x1
-$L21:
- lui x2,%hi(buf.1595)
- add x2,x2,%lo(buf.1595)
-$L15:
- lw x4,%lo(buflen.1596)(x3)
- li x5,4 # 0x4
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x5,0(x30)
- li x5,1 # 0x1
- sd x5,8(x30)
- sd x2,16(x30)
- sd x4,24(x30)
- fence
- #APP
- # 45 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L17:
- #APP
- # 46 "syscalls.c" 1
- mfpcr x2,cr31
- # 0 "" 2
- #NO_APP
- beq x2,x0,$L17
- move x2,x0
- sw x0,%lo(buflen.1596)(x3)
- add x30,x30,64
- j x1
- .end putchar
- .size putchar, .-putchar
- .align 2
- .globl exit
- .ent exit
- .type exit, @function
-exit:
- .frame x30,64,x1 # vars= 64, regs= 0/0, args= 0
- .mask 0x00000000,0
- .fmask 0x00000000,0
- add x30,x30,-64
- li x2,1 # 0x1
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x2,0(x30)
- sd x4,8(x30)
- fence
- #APP
- # 12 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L23:
- j $L23
- .end exit
- .size exit, .-exit
- .align 2
- .globl printstr
- .ent printstr
- .type printstr, @function
-printstr:
- .frame x30,80,x1 # vars= 64, regs= 1/0, args= 0
- .mask 0x00000002,-8
- .fmask 0x00000000,0
- add x30,x30,-80
- li x3,4 # 0x4
- sd x0,0(x30)
- sd x0,8(x30)
- sd x0,16(x30)
- sd x0,24(x30)
- sd x0,32(x30)
- sd x0,40(x30)
- sd x0,48(x30)
- sd x0,56(x30)
- sd x3,0(x30)
- li x3,1 # 0x1
- sd x3,8(x30)
- sd x1,72(x30)
- sd x4,16(x30)
- jal strlen
- sd x2,24(x30)
- fence
- #APP
- # 24 "syscalls.c" 1
- mtpcr x2,x30,cr30
- # 0 "" 2
- #NO_APP
-$L25:
- #APP
- # 25 "syscalls.c" 1
- mfpcr x2,cr31
- # 0 "" 2
- #NO_APP
- beq x2,x0,$L25
- ld x1,72(x30)
- add x30,x30,80
- j x1
- .end printstr
- .size printstr, .-printstr
- .align 2
- .globl printhex
- .ent printhex
- .type printhex, @function
-printhex:
- .frame x30,48,x1 # vars= 32, regs= 1/0, args= 0
- .mask 0x00000002,-8
- .fmask 0x00000000,0
- add x30,x30,-48
- sd x1,40(x30)
- add x2,x30,15
- add x7,x30,-1
-$L29:
- and x3,x4,15
- sltu x6,x3,10
- li x5,87 # 0x57
- beq x6,x0,$L28
- li x5,48 # 0x30
-$L28:
- add x3,x5,x3
- sb x3,0(x2)
- add x2,x2,-1
- srl x4,x4,4
- bne x2,x7,$L29
- move x4,x30
- sb x0,16(x30)
- jal printstr
- ld x1,40(x30)
- add x30,x30,48
- j x1
- .end printhex
- .size printhex, .-printhex
- .section .rodata.str1.8
- .align 3
-$LC1:
- .ascii "(null)\000"
- .text
- .align 2
- .globl vprintfmt
- .ent vprintfmt
- .type vprintfmt, @function
-vprintfmt:
- .frame x30,112,x1 # vars= 32, regs= 10/0, args= 0
- .mask 0x2ff00002,-8
- .fmask 0x00000000,0
- add x30,x30,-112
- sd x25,80(x30)
- lui x25,%hi($L53)
- sd x26,88(x30)
- sd x24,72(x30)
- sd x23,64(x30)
- sd x22,56(x30)
- sd x21,48(x30)
- sd x20,40(x30)
- sd x29,104(x30)
- sd x27,96(x30)
- sd x1,32(x30)
- move x21,x4
- move x20,x5
- move x23,x6
- sd x7,0(x30)
- li x22,37 # 0x25
- add x25,x25,%lo($L53)
- li x24,-1 # 0xffffffffffffffff
- lui x26,%hi($LC1)
- j $L84
-$L35:
- beq x2,x0,$L32
- move x5,x20
- add x23,x23,1
- jalr x21
-$L84:
- lbu x4,0(x23)
- move x2,x4
- bne x4,x22,$L35
- ld x2,0(x30)
- add x6,x23,1
- move x7,x6
- li x27,32 # 0x20
- sd x0,8(x30)
- li x3,-1 # 0xffffffffffffffff
- li x29,-1 # 0xffffffffffffffff
- move x5,x0
-$L85:
- lbu x4,0(x7)
- add x23,x7,1
- addw x8,x4,-35
- and x9,x8,0xff
- sltu x9,x9,86
- bne x9,x0,$L90
-$L38:
- li x4,37 # 0x25
- move x5,x20
- sd x2,0(x30)
- move x23,x6
- jalr x21
- j $L84
-$L32:
- ld x1,32(x30)
- ld x29,104(x30)
- ld x27,96(x30)
- ld x26,88(x30)
- ld x25,80(x30)
- ld x24,72(x30)
- ld x23,64(x30)
- ld x22,56(x30)
- ld x21,48(x30)
- ld x20,40(x30)
- add x30,x30,112
- j x1
-$L90:
- and x8,x8,0xff
- sll x8,x8,3
- add x8,x25,x8
- ld x8,0(x8)
- j x8
- .section .rodata
- .align 3
- .align 2
-$L53:
- .dword $L39
- .dword $L38
- .dword $L40
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L41
- .dword $L38
- .dword $L38
- .dword $L42
- .dword $L43
- .dword $L38
- .dword $L74
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L44
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L45
- .dword $L46
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L38
- .dword $L47
- .dword $L38
- .dword $L38
- .dword $L48
- .dword $L49
- .dword $L38
- .dword $L38
- .dword $L50
- .dword $L38
- .dword $L51
- .dword $L38
- .dword $L38
- .dword $L52
- .text
-$L52:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,16 # 0x10
-$L73:
- move x4,x21
- move x5,x20
- move x8,x29
- move x9,x27
- jal printnum
- j $L84
-$L39:
- li x4,1 # 0x1
- move x7,x23
- sd x4,8(x30)
- j $L85
-$L40:
- move x5,x20
- sd x2,0(x30)
- jalr x21
- j $L84
-$L41:
- lw x3,0(x2)
- move x7,x23
- add x2,x2,8
-$L54:
- bge x29,x0,$L85
- move x29,x3
- li x3,-1 # 0xffffffffffffffff
- j $L85
-$L42:
- move x7,x23
- li x27,45 # 0x2d
- j $L85
-$L43:
- blt x29,x0,$L91
- move x7,x23
- j $L85
-$L74:
- move x7,x23
- li x27,48 # 0x30
- j $L85
-$L44:
- lb x8,1(x7)
- addw x3,x4,-48
- move x7,x23
- addw x4,x8,-48
- sltu x4,x4,10
- beq x4,x0,$L54
-$L55:
- add x7,x7,1
- lb x4,0(x7)
- sllw x9,x3,1
- sllw x3,x3,3
- addw x3,x9,x3
- addw x9,x4,-48
- addw x3,x3,x8
- sltu x9,x9,10
- addw x3,x3,-48
- move x8,x4
- bne x9,x0,$L55
- j $L54
-$L45:
- lw x4,0(x2)
- add x2,x2,8
- move x5,x20
- sd x2,0(x30)
- jalr x21
- j $L84
-$L46:
- slt x3,x5,2
- bne x3,x0,$L69
-$L88:
- add x3,x2,8
- sd x3,0(x30)
- ld x6,0(x2)
- blt x6,x0,$L72
-$L89:
- li x7,10 # 0xa
- j $L73
-$L47:
- addw x5,x5,1
- move x7,x23
- j $L85
-$L48:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,8 # 0x8
- j $L73
-$L49:
- sd x2,0(x30)
- li x4,48 # 0x30
- move x5,x20
- jalr x21
- li x4,120 # 0x78
- move x5,x20
- jalr x21
- ld x2,0(x30)
- li x7,16 # 0x10
- add x3,x2,8
- sd x3,0(x30)
- ld x6,0(x2)
- j $L73
-$L50:
- add x4,x2,8
- sd x4,0(x30)
- ld x2,0(x2)
- sd x2,16(x30)
- beq x2,x0,$L92
-$L58:
- ble x29,x0,$L59
- li x2,45 # 0x2d
- beq x27,x2,$L59
- ld x4,16(x30)
- move x5,x3
- sd x3,24(x30)
- jal strnlen
- sllw x2,x2,0
- subw x2,x29,x2
- move x29,x2
- ld x3,24(x30)
- ble x2,x0,$L59
- move x29,x2
-$L60:
- sd x3,24(x30)
- move x4,x27
- move x5,x20
- addw x29,x29,-1
- jalr x21
- ld x3,24(x30)
- bne x29,x0,$L60
-$L59:
- ld x2,16(x30)
- lb x4,0(x2)
- add x27,x2,1
- beq x4,x0,$L62
-$L80:
- blt x3,x0,$L67
- addw x2,x3,-1
- move x3,x2
- beq x2,x24,$L62
-$L67:
- ld x2,8(x30)
- beq x2,x0,$L63
- addw x2,x4,-32
- sltu x2,x2,95
- beq x2,x0,$L93
-$L63:
- sd x3,24(x30)
- move x5,x20
- jalr x21
- ld x3,24(x30)
-$L64:
- lb x4,0(x27)
- addw x29,x29,-1
- add x27,x27,1
- bne x4,x0,$L80
-$L62:
- ble x29,x0,$L84
-$L79:
- addw x29,x29,-1
- li x4,32 # 0x20
- move x5,x20
- jalr x21
- bne x29,x0,$L79
- j $L84
-$L51:
- move x4,x30
- sd x2,0(x30)
- jal getuint
- move x6,x2
- li x7,10 # 0xa
- j $L73
-$L93:
- sd x3,24(x30)
- li x4,63 # 0x3f
- move x5,x20
- jalr x21
- ld x3,24(x30)
- j $L64
-$L91:
- move x7,x23
- move x29,x0
- j $L85
-$L92:
- add x2,x26,%lo($LC1)
- sd x2,16(x30)
- j $L58
-$L72:
- sd x6,24(x30)
- li x4,45 # 0x2d
- move x5,x20
- jalr x21
- ld x6,24(x30)
- li x7,10 # 0xa
- sub x6,zero,x6
- j $L73
-$L69:
- bne x5,x0,$L88
- lw x6,0(x2)
- add x2,x2,8
- sd x2,0(x30)
- bge x6,x0,$L89
- j $L72
- .end vprintfmt
- .size vprintfmt, .-vprintfmt
- .align 2
- .globl printf
- .ent printf
- .type printf, @function
-printf:
- .frame x30,96,x1 # vars= 16, regs= 1/0, args= 0
- .mask 0x00000002,-72
- .fmask 0x00000000,0
- add x30,x30,-96
- add x2,x30,40
- move x3,x4
- lui x4,%hi(putchar)
- sd x5,40(x30)
- sd x6,48(x30)
- sd x7,56(x30)
- add x4,x4,%lo(putchar)
- move x5,x0
- move x6,x3
- move x7,x2
- sd x1,24(x30)
- sd x8,64(x30)
- sd x9,72(x30)
- sd x10,80(x30)
- sd x11,88(x30)
- sd x2,0(x30)
- jal vprintfmt
- li x4,-1 # 0xffffffffffffffff
- jal putchar
- ld x1,24(x30)
- move x2,x0
- add x30,x30,96
- j x1
- .end printf
- .size printf, .-printf
- .local buflen.1596
- .comm buflen.1596,4,4
- .local buf.1595
- .comm buf.1595,64,8
- .ident "GCC: (GNU) 4.6.1"
+++ /dev/null
-#include <stdint.h>
-#include <string.h>
-#include <stdarg.h>
-#include "pcr.h"
-
-void exit(int code)
-{
- volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 1;
- magic_mem[1] = code;
- __sync_synchronize();
- mtpcr(PCR_TOHOST, (long)magic_mem);
- while(1);
-}
-
-void printstr(const char* s)
-{
- volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 4;
- magic_mem[1] = 1;
- magic_mem[2] = (unsigned long)s;
- magic_mem[3] = strlen(s);
- __sync_synchronize();
- mtpcr(PCR_TOHOST, (long)magic_mem);
- while(mtpcr(PCR_FROMHOST, 0) == 0);
-}
-
-int putchar(int ch)
-{
- #define buffered_putch_bufsize 64
- static char buf[buffered_putch_bufsize];
- static int buflen = 0;
-
- if(ch != -1)
- buf[buflen++] = ch;
-
- if(ch == -1 || buflen == buffered_putch_bufsize)
- {
- volatile uint64_t magic_mem[8] = {0};
- magic_mem[0] = 4;
- magic_mem[1] = 1;
- magic_mem[2] = (long)buf;
- magic_mem[3] = buflen;
- __sync_synchronize();
- mtpcr(PCR_TOHOST, (long)magic_mem);
- while(mtpcr(PCR_FROMHOST, 0) == 0);
-
- buflen = 0;
- }
-
- return 0;
-}
-
-void printhex(uint64_t x)
-{
- char str[17];
- int i;
- for (i = 0; i < 16; i++)
- {
- str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
- x >>= 4;
- }
- str[16] = 0;
-
- printstr(str);
-}
-
-static void printnum(void (*putch)(int, void**), void **putdat,
- unsigned long long num, unsigned base, int width, int padc)
-{
- if (num >= base)
- printnum(putch, putdat, num / base, base, width - 1, padc);
- else while (--width > 0)
- putch(padc, putdat);
-
- putch("0123456789abcdef"[num % base], putdat);
-}
-
-static unsigned long long getuint(va_list *ap, int lflag)
-{
- if (lflag >= 2)
- return va_arg(*ap, unsigned long long);
- else if (lflag)
- return va_arg(*ap, unsigned long);
- else
- return va_arg(*ap, unsigned int);
-}
-
-static long long getint(va_list *ap, int lflag)
-{
- if (lflag >= 2)
- return va_arg(*ap, long long);
- else if (lflag)
- return va_arg(*ap, long);
- else
- return va_arg(*ap, int);
-}
-
-void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
-{
- register const char* p;
- const char* last_fmt;
- register int ch, err;
- unsigned long long num;
- int base, lflag, width, precision, altflag;
- char padc;
-
- while (1) {
- while ((ch = *(unsigned char *) fmt) != '%') {
- if (ch == '\0')
- return;
- fmt++;
- putch(ch, putdat);
- }
- fmt++;
-
- // Process a %-escape sequence
- last_fmt = fmt;
- padc = ' ';
- width = -1;
- precision = -1;
- lflag = 0;
- altflag = 0;
- reswitch:
- switch (ch = *(unsigned char *) fmt++) {
-
- // flag to pad on the right
- case '-':
- padc = '-';
- goto reswitch;
-
- // flag to pad with 0's instead of spaces
- case '0':
- padc = '0';
- goto reswitch;
-
- // width field
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- for (precision = 0; ; ++fmt) {
- precision = precision * 10 + ch - '0';
- ch = *fmt;
- if (ch < '0' || ch > '9')
- break;
- }
- goto process_precision;
-
- case '*':
- precision = va_arg(ap, int);
- goto process_precision;
-
- case '.':
- if (width < 0)
- width = 0;
- goto reswitch;
-
- case '#':
- altflag = 1;
- goto reswitch;
-
- process_precision:
- if (width < 0)
- width = precision, precision = -1;
- goto reswitch;
-
- // long flag (doubled for long long)
- case 'l':
- lflag++;
- goto reswitch;
-
- // character
- case 'c':
- putch(va_arg(ap, int), putdat);
- break;
-
- // string
- case 's':
- if ((p = va_arg(ap, char *)) == NULL)
- p = "(null)";
- if (width > 0 && padc != '-')
- for (width -= strnlen(p, precision); width > 0; width--)
- putch(padc, putdat);
- for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
- if (altflag && (ch < ' ' || ch > '~'))
- putch('?', putdat);
- else
- putch(ch, putdat);
- p++;
- }
- for (; width > 0; width--)
- putch(' ', putdat);
- break;
-
- // (signed) decimal
- case 'd':
- num = getint(&ap, lflag);
- if ((long long) num < 0) {
- putch('-', putdat);
- num = -(long long) num;
- }
- base = 10;
- goto number;
-
- // unsigned decimal
- case 'u':
- num = getuint(&ap, lflag);
- base = 10;
- goto number;
-
- // (unsigned) octal
- case 'o':
- // should do something with padding so it's always 3 octits
- num = getuint(&ap, lflag);
- base = 8;
- goto number;
-
- // pointer
- case 'p':
- putch('0', putdat);
- putch('x', putdat);
- num = (unsigned long long)
- (uintptr_t) va_arg(ap, void *);
- base = 16;
- goto number;
-
- // (unsigned) hexadecimal
- case 'x':
- num = getuint(&ap, lflag);
- base = 16;
- number:
- printnum(putch, putdat, num, base, width, padc);
- break;
-
- // escaped '%' character
- case '%':
- putch(ch, putdat);
- break;
-
- // unrecognized escape sequence - just print it literally
- default:
- putch('%', putdat);
- fmt = last_fmt;
- break;
- }
- }
-}
-
-int printf(const char* fmt, ...)
-{
- va_list ap;
- va_start(ap, fmt);
-
- vprintfmt((void*)putchar, 0, fmt, ap);
- putchar(-1);
-
- va_end(ap);
- return 0; // incorrect return value, but who cares, anyway?
-}
+++ /dev/null
-/*======================================================================*/
-/* Proxy kernel linker script */
-/*======================================================================*/
-/* This is the linker script used when building the proxy kernel. */
-
-/*----------------------------------------------------------------------*/
-/* Setup */
-/*----------------------------------------------------------------------*/
-
-/* The OUTPUT_ARCH command specifies the machine architecture where the
- argument is one of the names used in the BFD library. More
- specifically one of the entires in bfd/cpu-mips.c */
-
-OUTPUT_ARCH( "riscv" )
-
-/* The ENTRY command specifies the entry point (ie. first instruction
- to execute). The symbol _start should be defined in each test. */
-
-ENTRY( _start )
-
-/*----------------------------------------------------------------------*/
-/* Sections */
-/*----------------------------------------------------------------------*/
-
-SECTIONS
-{
-
- /* text: test code section */
- . = 0x00002000;
- .text :
- {
- crt-mt.o(.text)
- *(.text)
- }
-
- /* data: Initialized data segment */
- .data :
- {
- *(.data)
- }
-
- /* End of uninitalized data segement */
- _end = .;
-}
-
+++ /dev/null
-/*======================================================================*/
-/* Proxy kernel linker script */
-/*======================================================================*/
-/* This is the linker script used when building the proxy kernel. */
-
-/*----------------------------------------------------------------------*/
-/* Setup */
-/*----------------------------------------------------------------------*/
-
-/* The OUTPUT_ARCH command specifies the machine architecture where the
- argument is one of the names used in the BFD library. More
- specifically one of the entires in bfd/cpu-mips.c */
-
-OUTPUT_ARCH( "riscv" )
-
-/* The ENTRY command specifies the entry point (ie. first instruction
- to execute). The symbol _start should be defined in each test. */
-
-ENTRY( _start )
-
-/*----------------------------------------------------------------------*/
-/* Sections */
-/*----------------------------------------------------------------------*/
-
-SECTIONS
-{
-
- /* text: test code section */
- . = 0x00002000;
- .text :
- {
- crt.o(.text)
- *(.text)
- }
-
- /* data: Initialized data segment */
- .data :
- {
- *(.data)
- }
-
- /* End of uninitalized data segement */
- _end = .;
-}
-
+++ /dev/null
-// helpful utility and synch functions
-
-// relies on defining "ncores" before including this file...
-
-#ifndef __UTIL_H
-#define __UTIL_H
-
-#define rdcycle() ({ unsigned long _c; asm volatile ("rdcycle %0" : "=r"(_c) :: "memory"); _c; })
-#define rdinstret() ({ unsigned long _c; asm volatile ("rdinstret %0" : "=r"(_c) :: "memory"); _c; })
-
-void __attribute__((noinline)) barrier()
-{
- static volatile int sense;
- static volatile int count;
- static __thread int threadsense;
-
- __sync_synchronize();
-
- threadsense = !threadsense;
- if (__sync_fetch_and_add(&count, 1) == ncores-1)
- {
- count = 0;
- sense = threadsense;
- }
- else while(sense != threadsense)
- ;
-
- __sync_synchronize();
-}
-
-#endif //__UTIL_H
-
projects / riscv-tests.git / commitdiff