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Merge pull request #52 from riscv/vcs_sim_cmd
authorMegan Wachs <megan@sifive.com>
Thu, 18 May 2017 19:14:07 +0000 (12:14 -0700)
committerGitHub <noreply@github.com>
Thu, 18 May 2017 19:14:07 +0000 (12:14 -0700)
debug: Correct the calling for a 32-bit simulation target


Trivial merge