make rv32si fault load/store test stronger

diff --git a/isa/rv32si/fa_addr_zscale_8192.S b/isa/rv32si/fa_addr_zscale_8192.S
index 8bb110af24e746b4293566adcc5dcca9aa826eb0..37b6edf02b75a3c9b1fbbb26c991ea16b3cf7d4e 100644 (file)
--- a/isa/rv32si/fa_addr_zscale_8192.S
+++ b/isa/rv32si/fa_addr_zscale_8192.S
@@ -58,7 +58,11 @@ loop:
   li s0, 0xbad1dea0
   beq s1, x0, loop
 
-  j pass
+  li TESTNUM, 10
+  li s0, 0x1ffc
+  lw x0, 0(s0) // if an exception is taken, then would fail because evec is set to evec_store
+
+  j pass // this time it should pass
 
   TEST_PASSFAIL