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Fix ma_fetch to work with or without RVC
author
Andrew Waterman
<waterman@cs.berkeley.edu>
Thu, 3 Mar 2016 05:42:17 +0000
(21:42 -0800)
committer
Andrew Waterman
<waterman@cs.berkeley.edu>
Thu, 3 Mar 2016 19:03:59 +0000
(11:03 -0800)
isa/rv64si/ma_fetch.S
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diff --git
a/isa/rv64si/ma_fetch.S
b/isa/rv64si/ma_fetch.S
index 272a9eba7d2b596e3ad782349a570dd20cd004b8..db702d96773c8ba7cc03eddc291cb46dbec99770 100644
(file)
--- a/
isa/rv64si/ma_fetch.S
+++ b/
isa/rv64si/ma_fetch.S
@@
-21,14
+21,21
@@
RVTEST_CODE_BEGIN
#define stvec_handler mtvec_handler
#endif
#define stvec_handler mtvec_handler
#endif
-#ifndef __rvc
+ .option norvc
+
+ # Without RVC, the jalr should trap, and the handler will skip ahead.
+ # With RVC, the jalr should not trap, and "j fail" should get skipped.
li TESTNUM, 2
li t1, 0
la t0, 1f
jalr t1, t0, 2
1:
li TESTNUM, 2
li t1, 0
la t0, 1f
jalr t1, t0, 2
1:
+ .option rvc
+ c.j fail
+ c.j 2f
+ .option norvc
j fail
j fail
-#endif
+2:
// This test should pass, since JALR ignores the target LSB
li TESTNUM, 3
// This test should pass, since JALR ignores the target LSB
li TESTNUM, 3
@@
-39,14
+46,17
@@
RVTEST_CODE_BEGIN
j fail
1:
j fail
1:
-#ifndef __rvc
li TESTNUM, 4
li t1, 0
li TESTNUM, 4
li t1, 0
- la t0, 3f
- jr t0, 3
-3:
+ la t0, 1f
+ jalr t1, t0, 3
+1:
+ .option rvc
+ c.j fail
+ c.j 2f
+ .option norvc
j fail
j fail
-#endif
+2:
j pass
j pass
@@
-74,7
+84,7
@@
stvec_handler:
addi t0, t0, -4
bne t0, a1, fail
addi t0, t0, -4
bne t0, a1, fail
- addi a1, a1,
8
+ addi a1, a1,
12
csrw sepc, a1
sret
csrw sepc, a1
sret