correctly set SR_EA bit for all vector physical tests

diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h
index d9b23fb60e4d1f3b0782257351aeb25d7ad6a893..20d06900cf9ec244fea52e7226296dedba840faa 100644 (file)
--- a/env/v/riscv_test.h
+++ b/env/v/riscv_test.h
@@ -12,9 +12,10 @@
 #define RVTEST_RV64UF                                                   \
   .macro init;                                                          \
   fssr x0;                                                              \
-  .endm 
+  .endm
 
-#define RVTEST_VEC_ENABLE                                               \
+#define RVTEST_RV64UV                                                   \
+       RVTEST_RV64UF
 
 #define RVTEST_CODE_BEGIN                                               \
         .text;                                                          \

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 6cfda128364602e032cabbeb9060814784b7f00d..59e9e77bcb1a250fa66cc8ce401cb827d328c372 100644 (file)
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -1,6 +1,8 @@
 #ifndef __TEST_MACROS_VECTOR_H
 #define __TEST_MACROS_VECTOR_H
 
+#undef EXTRA_INIT
+#define EXTRA_INIT RVTEST_VEC_ENABLE
 
 #-----------------------------------------------------------------------
 # Helper macros

diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index ce3c6a6635364f1e6ef8e13f3b1047dca0acbe2c..68b0ba15843873f2e8c3af8d74e645c51784a4b8 100644 (file)
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
index 2bf010f5a86be0a242407f99fbbaec6a90cce04f..ba798eff49abf4da2c7c559b57500e702391a3cf 100644 (file)
--- a/isa/rv64uv/amoadd_w.S
+++ b/isa/rv64uv/amoadd_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
index 2652fbe8d08350f986ec582b587420750ff88cd6..b2dc699f61a1bdba87ffc2b4f0ee9744ba60fc3c 100644 (file)
--- a/isa/rv64uv/amoand_d.S
+++ b/isa/rv64uv/amoand_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
index 93f660f53eccbe88125aff701d5abd79783bd81f..726033d4b797553da8ff1a2b71c94ab77553236e 100644 (file)
--- a/isa/rv64uv/amoand_w.S
+++ b/isa/rv64uv/amoand_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
index 97a5cf4e25cfdb72de154cadd9d8245ae7b9adb7..aafdf7548f68fabd4e8be6f7e11c6ff07d205084 100644 (file)
--- a/isa/rv64uv/amomax_d.S
+++ b/isa/rv64uv/amomax_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index f89bed6699bab28eaeb2d983ad0a500b0dc64d03..0308991ebfe557a63be97d082fcdbe3521b62c00 100644 (file)
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
index 679c04dae74bfc141853bf279f612e117915036f..95d8fce64213d91ef89d5555f6750f18258694ee 100644 (file)
--- a/isa/rv64uv/amomaxu_d.S
+++ b/isa/rv64uv/amomaxu_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
index 342d931c04e1fd8abbb2591b465546584b957a06..feac563418b2af9ab4c4ce34701237abece6acf1 100644 (file)
--- a/isa/rv64uv/amomaxu_w.S
+++ b/isa/rv64uv/amomaxu_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index c8dd43e6026c90572f129873a0af4b7beec0c425..6fd9d2739dcbfdd719d53b87f63a4dd8499e79b5 100644 (file)
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
index 0633ba7a47243143c1c743a42829c15fa2b55a67..44260f2e1ffca1074c5e5a743a6cd033b431eeac 100644 (file)
--- a/isa/rv64uv/amomin_w.S
+++ b/isa/rv64uv/amomin_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
index 13fa5f22f9b58613d00ab007f1b8c1747c2e019d..3f5f7abf74a8a232c5a3e85f44fd121c3822f90b 100644 (file)
--- a/isa/rv64uv/amominu_d.S
+++ b/isa/rv64uv/amominu_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 329b3549daf7e512ae66443191bb81909dc2561e..56f3a7dc68b69e89ee87e397e98bbb0845ea512d 100644 (file)
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index 800550deea334f3460fa9d1ff5feb6c67868415d..76d553c7bbdbe8ea111e3f1c86cd764d12c06208 100644 (file)
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 7fa683ab3d2b3a735d4c2732685c45c00a33776c..9d0bd2fc6a04316e4d37f30e66ce7284dc672b22 100644 (file)
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
index 6a33b1f5fa06c82ba5d8ad0af0f7a2ecea336aa1..df9855637035bfacd3eba5856a43559851907060 100644 (file)
--- a/isa/rv64uv/amoswap_d.S
+++ b/isa/rv64uv/amoswap_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
index 3ba51cbfdf5e1dd60ba03702d99a79610964caa7..c06856923db4f1a320c9b74fefae9ab920dfbab4 100644 (file)
--- a/isa/rv64uv/amoswap_w.S
+++ b/isa/rv64uv/amoswap_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/beq.S b/isa/rv64uv/beq.S
index aa6f2ffc5cb71168c7a9a8b16d0d796d144a2ff2..c2f7a56710997819347fee2dd52a05c6a2a4c918 100644 (file)
--- a/isa/rv64uv/beq.S
+++ b/isa/rv64uv/beq.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/bge.S b/isa/rv64uv/bge.S
index 06d15de3b47a726f50e41d6a802fdf4acc9e7006..165dbe8060ba3f7d8955978eeab2a53f323170a3 100644 (file)
--- a/isa/rv64uv/bge.S
+++ b/isa/rv64uv/bge.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/bgeu.S b/isa/rv64uv/bgeu.S
index 5f546702a170f5d27c9582919a68311468a4cfe9..551456fa456f9df90c9384a08e40e9a420bb452b 100644 (file)
--- a/isa/rv64uv/bgeu.S
+++ b/isa/rv64uv/bgeu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/blt.S b/isa/rv64uv/blt.S
index 913c55f3272bc50c97635a7bcbc548b5c48cfcc7..787d64debe0e48717ee913ebcdf56290b4f5cbab 100644 (file)
--- a/isa/rv64uv/blt.S
+++ b/isa/rv64uv/blt.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/bltu.S b/isa/rv64uv/bltu.S
index 562979130040f17b551424510006e2db62f7bb58..c187efdf05208fe23fb3b83b3de23ed070efc96b 100644 (file)
--- a/isa/rv64uv/bltu.S
+++ b/isa/rv64uv/bltu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/bne.S b/isa/rv64uv/bne.S
index a6b2347a817dbab7ceb3ea658838921a6fb55de9..ab31b6d12d03c860aff529e8d1c854ec915e9593 100644 (file)
--- a/isa/rv64uv/bne.S
+++ b/isa/rv64uv/bne.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
index 180712f74de7bfff811bad720333bc7579af060d..227a154ce9fa110a35c90cb7336304e93e4891b5 100644 (file)
--- a/isa/rv64uv/fcvt.S
+++ b/isa/rv64uv/fcvt.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32

diff --git a/isa/rv64uv/fence.S b/isa/rv64uv/fence.S
index 7e9b90ede63e707c0e5ebed2d216aec6282e68e1..5e8072c5e8a7f6e23db6a2180a192f92cff0c162 100644 (file)
--- a/isa/rv64uv/fence.S
+++ b/isa/rv64uv/fence.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning

diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index c86fbc9ac8a7c41bfdd408601e209b5f5369cc8d..d41e76122a80d2e7c7bf09b20c33024ce9e5f367 100644 (file)
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1

diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index d9e6da4ab3bd325119d88b42c85def9e6ee23911..7e940f6db82fc33e6f19b0175bb5ee5e46dc9d60 100644 (file)
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1

diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
index ab6f91c999257ad7b84cf3bc6e183a0b77290e5d..e875c61924ea785279da4dbf4677d85e1bde630e 100644 (file)
--- a/isa/rv64uv/fma.S
+++ b/isa/rv64uv/fma.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64UF
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,2

diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index a943326c5086eff00a4001993f3c70db4c4c12b2..47a6a3936d5e20ed291d89e91c81177ae16ed5bf 100644 (file)
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,2

diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
index 9142cf0b92f4662bb6a13836f2909e7f800e8618..f3e09b65f18b44f58136730b708ad7ec0393ba7f 100644 (file)
--- a/isa/rv64uv/fmovz.S
+++ b/isa/rv64uv/fmovz.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,2

diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
index b6b60fece386f2cc5b5e9138984cda1ff1e7c0b0..f22067988f74bcd35229e1e594630874774a4c27 100644 (file)
--- a/isa/rv64uv/fsd.S
+++ b/isa/rv64uv/fsd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1

diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index eaafeff4bc4a92b3fc5d1fe0b9399f9ea5a66afd..71c1d2f057a7ae4bf8cec86dde715e6070c6685a 100644 (file)
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1

diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index 0925e59de724db46b6c513e83dab2898bc8ebe67..1b3a2dd71a70b1dda7e3dd1164ab586d93a38b2a 100644 (file)
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0

diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
index 7e20b65ccd3efdec5690fb21cc070f0a8307213b..46ca639b09ab0a21d4cd3f800f727b333ca7b341 100644 (file)
--- a/isa/rv64uv/lb.S
+++ b/isa/rv64uv/lb.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 166f40e7f8b754f04c82f161c8151d3ec6710120..47c226151c0c1b5b12431c69455af1d0a6e37ee1 100644 (file)
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index a2f6b891d19bda5becd234b0e4cbd97fa8869990..354ee38531f87e329acb5b3da19e8e83ba5cb0d6 100644 (file)
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
index 910ffd35a877c056ffec82668a48dca933958995..e4ff17663821bf7cf0ec76fe7e00f52f08e559b5 100644 (file)
--- a/isa/rv64uv/lh.S
+++ b/isa/rv64uv/lh.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
index 7d4fb5ab097dab0bfc167362b87505c71bdc1f0c..dadf99be349c01872d3abc44413cd79bf002b2c7 100644 (file)
--- a/isa/rv64uv/lhu.S
+++ b/isa/rv64uv/lhu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 8b1563645d931c18d418562b35339cdd866f6d76..182dc8952e522d8feb140b9fc55c26f6ed2a38d7 100644 (file)
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index 6cbb30276610c08d3b2c7af43548ff834278730b..d6df8396ae9f647b2f09c3e9b8dfa40e0b4633b9 100644 (file)
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S
index 84bb27ef25d5ecde4e7a08b190e5e0b33c289a2a..df9b83832eb441f702ea08614fba90e5f206f32d 100644 (file)
--- a/isa/rv64uv/movn.S
+++ b/isa/rv64uv/movn.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
index 93328116516c74592d77f31458751cade1ea2eaf..374b271c378406971f6522430ff31d7f384e5cc1 100644 (file)
--- a/isa/rv64uv/movz.S
+++ b/isa/rv64uv/movz.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0

diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index 9155de9a1584f9836e1f08520e05f74ea5798f12..5cbe76aeb7feaca09ac7dbd257c790e8f91a5ee1 100644 (file)
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index 67b336c0165cad62981a0294b6649d45c43314aa..053c401fe24b8b7bf96e21c7c474dbcb98acf693 100644 (file)
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index e35a77b2ea552bad4164c2ab53a0e0c9ef6a6c43..25bb258dbe4b893d104a9232b2aa8e7fcac8303e 100644 (file)
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 6f883ffe219816debbfd39347e1dd79c23e954d2..8f1599b72893f5d3662e7ba6ddf655ff54c07984 100644 (file)
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0

diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 7de7a20c7c3a722eda106e6dbf16cbf6d876550f..04391151af7c6a356c48207b3f59fa0225aa02a0 100644 (file)
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 2,0

diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 6154620b8762a9eca2edf43689edcd72485157a2..68e085ea14f79893308b6165305f0ba76d144ad9 100644 (file)
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 2,2

diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
index b66288c23ea18e77d953d8f1ef6f99a112017075..d469e59b5e86f65176390a1aa56f81aca645582c 100644 (file)
--- a/isa/rv64uv/vmsv.S
+++ b/isa/rv64uv/vmsv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0

diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index 3b316b96a222ed79d01982040d6363636efa8f2a..be1adb3c07b2cfba4880bb5d37cf4040e00320f2 100644 (file)
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 3,0

diff --git a/isa/rv64uv/vsetcfg.S b/isa/rv64uv/vsetcfg.S
index 896278297900c5b13af11c12b7c228055cfd7b08..f0f532e601dee9da4d39fef70cdfcea072bf24c2 100644 (file)
--- a/isa/rv64uv/vsetcfg.S
+++ b/isa/rv64uv/vsetcfg.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/vsetcfgi.S b/isa/rv64uv/vsetcfgi.S
index 56e30ff0ce66bf9c483a1a65edc7d88022fabe3f..18f32949ee179972e2b47053d5122b4b3ec7c134 100644 (file)
--- a/isa/rv64uv/vsetcfgi.S
+++ b/isa/rv64uv/vsetcfgi.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/vsetvl.S b/isa/rv64uv/vsetvl.S
index 019439ae8dbb1045f13b9662912a8c117fed8ca6..1897ebfce258b4a0a5787d7d955d52552f61f99f 100644 (file)
--- a/isa/rv64uv/vsetvl.S
+++ b/isa/rv64uv/vsetvl.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 539ba92093c31227dc2f74bb2d0f6dcfcb973e40..5f9f3a424c1a448e5d44b25a9b605f6fb8c58ffb 100644 (file)
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0

diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
index bf032fa22a5a41dc00c8f27e8f8a0d323c290f4c..8875b9565f7b1071fcbc63d945b0e3a7461dfa2d 100644 (file)
--- a/isa/rv64uv/vvadd_d.S
+++ b/isa/rv64uv/vvadd_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0

diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 7b2ce98ea2e32898d2221b85a7e5ae7685a214d7..2912b70698e2de5213e4484e6953a637f2806956 100644 (file)
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32

diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
index 0b3138bd3d8fdd4998d2fcb0c22c755087e1521d..571c4573f07139952e425dea96622183a08eaff8 100644 (file)
--- a/isa/rv64uv/vvadd_fw.S
+++ b/isa/rv64uv/vvadd_fw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32

diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index 6e194b22fe6ebc8c3616814127e4c8661c3b462d..f81c42e07a08f895cfa73ddd56dee5b74f13f2bf 100644 (file)
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0

diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
index 335fe3b97c29e22ae1b8bb5e8b2bd22bc63863d5..a6a9d4a4fdab743f56fae24c53ab430412fc1f64 100644 (file)
--- a/isa/rv64uv/vvmul_d.S
+++ b/isa/rv64uv/vvmul_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0

diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
index 9fadeba20af3d092b8ce54a09b3a683ce742908b..008423a28cd29d9bf49f71ea5da8032d90d0695c 100644 (file)
--- a/isa/rv64uv/wakeup.S
+++ b/isa/rv64uv/wakeup.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning