Don't use stats register; refer to uarch counters by number
authorAndrew Waterman <waterman@cs.berkeley.edu>
Wed, 6 Apr 2016 17:29:08 +0000 (10:29 -0700)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Wed, 6 Apr 2016 17:29:08 +0000 (10:29 -0700)
benchmarks/common/syscalls.c
env

index d391013450b10cb22401de1ca551f38ca4483234..87fd358ce0c17c2cb110254a6057cdaf9a8b49ce 100644 (file)
@@ -39,9 +39,6 @@ static long counters[NUM_COUNTERS];
 static char* counter_names[NUM_COUNTERS];
 static int handle_stats(int enable)
 {
 static char* counter_names[NUM_COUNTERS];
 static int handle_stats(int enable)
 {
-  //use csrs to set stats register
-  if (enable)
-    asm volatile ("csrrs a0, stats, 1" ::: "a0");
   int i = 0;
 #define READ_CTR(name) do { \
     while (i >= NUM_COUNTERS) ; \
   int i = 0;
 #define READ_CTR(name) do { \
     while (i >= NUM_COUNTERS) ; \
@@ -50,13 +47,11 @@ static int handle_stats(int enable)
     counters[i++] = csr; \
   } while (0)
   READ_CTR(mcycle);  READ_CTR(minstret);
     counters[i++] = csr; \
   } while (0)
   READ_CTR(mcycle);  READ_CTR(minstret);
-  READ_CTR(uarch0);  READ_CTR(uarch1);  READ_CTR(uarch2);  READ_CTR(uarch3);
-  READ_CTR(uarch4);  READ_CTR(uarch5);  READ_CTR(uarch6);  READ_CTR(uarch7);
-  READ_CTR(uarch8);  READ_CTR(uarch9);  READ_CTR(uarch10); READ_CTR(uarch11);
-  READ_CTR(uarch12); READ_CTR(uarch13); READ_CTR(uarch14); READ_CTR(uarch15);
+  READ_CTR(0xcc0); READ_CTR(0xcc1); READ_CTR(0xcc2); READ_CTR(0xcc3);
+  READ_CTR(0xcc4); READ_CTR(0xcc5); READ_CTR(0xcc6); READ_CTR(0xcc7);
+  READ_CTR(0xcc8); READ_CTR(0xcc9); READ_CTR(0xcca); READ_CTR(0xccb);
+  READ_CTR(0xccc); READ_CTR(0xccd); READ_CTR(0xcce); READ_CTR(0xccf);
 #undef READ_CTR
 #undef READ_CTR
-  if (!enable)
-    asm volatile ("csrrc a0, stats, 1" ::: "a0");
   return 0;
 }
 
   return 0;
 }
 
@@ -69,7 +64,7 @@ void tohost_exit(long code)
 long handle_trap(long cause, long epc, long regs[32])
 {
   int* csr_insn;
 long handle_trap(long cause, long epc, long regs[32])
 {
   int* csr_insn;
-  asm ("jal %0, 1f; csrr a0, 0x0; 1:" : "=r"(csr_insn));
+  asm ("jal %0, 1f; csrr a0, 0xcc0; 1:" : "=r"(csr_insn));
   long sys_ret = 0;
 
   if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
   long sys_ret = 0;
 
   if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
diff --git a/env b/env
index ef1457fa7a3bf3fd58dadd0f30002828b353e573..0fc840489c21530a8bfdaecac1131fcd20bdaea2 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit ef1457fa7a3bf3fd58dadd0f30002828b353e573
+Subproject commit 0fc840489c21530a8bfdaecac1131fcd20bdaea2