isa_src_dir := $(abs_top_src_dir)/isa
debug_src_dir := $(abs_top_src_dir)/debug
-all: benchmarks isa
+all: benchmarks isa debug
install: all
install -d $(instbasedir)/share/riscv-tests/isa
`./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
-32-bit SiFive Core on Microsemi FPGA board
-------------------------------------------
+32-bit SiFive Core on Arty FPGA board
+-------------------------------------
-`./gdbserver.py --m2gl_m2s`
+`./gdbserver.py --freedom-e300`
Debug Tips
==========
You can see what spike is doing by add `-l` to the spike command, eg.:
`./gdbserver.py --spike32 --cmd "$RISCV/bin/spike -l"
DebugTest.test_breakpoint`. (Then look at spike.log.)
+
+You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py --spike64
+--gdb "valgrind riscv64-unknown-elf-gdb" -- -v DownloadTest`.
MSTATUS32_SD = 0x80000000
MSTATUS64_SD = 0x8000000000000000
+def gdb():
+ if parsed.gdb:
+ return testlib.Gdb(parsed.gdb)
+ else:
+ return testlib.Gdb()
+
def ihex_line(address, record_type, data):
assert len(data) < 128
line = ":%02X%04X%02X" % (len(data), address, record_type)
class SimpleRegisterTest(DeleteServer):
def setUp(self):
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
# For now gdb has to be told what the architecture is when it's not
# given an ELF file.
self.gdb.command("set arch riscv:rv%d" % target.xlen)
class SimpleMemoryTest(DeleteServer):
def setUp(self):
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("set arch riscv:rv%d" % target.xlen)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
class InstantHaltTest(DeleteServer):
def setUp(self):
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("set arch riscv:rv%d" % target.xlen)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
self.binary = target.compile("programs/debug.c", "programs/checksum.c",
"programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("file %s" % self.binary)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
self.gdb.load()
def setUp(self):
self.binary = target.compile("programs/step.S")
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("file %s" % self.binary)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
self.gdb.load()
def setUp(self):
self.binary = target.compile("programs/regs.S")
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("file %s" % self.binary)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
self.gdb.load()
self.binary = target.compile(download_c.name, "programs/checksum.c")
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("file %s" % self.binary)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
def setUp(self):
self.binary = target.compile("programs/mprv.S")
self.server = target.server()
- self.gdb = testlib.Gdb()
+ self.gdb = gdb()
self.gdb.command("file %s" % self.binary)
self.gdb.command("target extended-remote localhost:%d" % self.server.port)
self.gdb.load()
output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
self.assertIn("0xbead", output)
+class PrivTest(DeleteServer):
+ def setUp(self):
+ self.binary = target.compile("programs/priv.S")
+ self.server = target.server()
+ self.gdb = gdb()
+ self.gdb.command("file %s" % self.binary)
+ self.gdb.command("target extended-remote localhost:%d" % self.server.port)
+ self.gdb.load()
+
+ misa = self.gdb.p("$misa")
+ self.supported = set()
+ if misa & (1<<20):
+ self.supported.add(0)
+ if misa & (1<<18):
+ self.supported.add(1)
+ if misa & (1<<7):
+ self.supported.add(2)
+ self.supported.add(3)
+
+ def test_rw(self):
+ """Test reading/writing priv."""
+ for privilege in range(4):
+ self.gdb.p("$priv=%d" % privilege)
+ self.gdb.stepi()
+ actual = self.gdb.p("$priv")
+ self.assertIn(actual, self.supported)
+ if privilege in self.supported:
+ self.assertEqual(actual, privilege)
+
+ def test_change(self):
+ """Test that the core's privilege level actually changes."""
+
+ if 0 not in self.supported:
+ # TODO: return not applicable
+ return
+
+ self.gdb.b("main")
+ self.gdb.c()
+
+ # Machine mode
+ self.gdb.p("$priv=3")
+ main = self.gdb.p("$pc")
+ self.gdb.stepi()
+ self.assertEqual("%x" % self.gdb.p("$pc"), "%x" % (main+4))
+
+ # User mode
+ self.gdb.p("$priv=0")
+ self.gdb.stepi()
+ # Should have taken an exception, so be nowhere near main.
+ pc = self.gdb.p("$pc")
+ self.assertTrue(pc < main or pc > main + 0x100)
+
class Target(object):
directory = None
dest="target")
parser.add_argument("--cmd",
help="The command to use to start the debug server.")
+ parser.add_argument("--gdb",
+ help="The command to use to start gdb.")
parser.add_argument("--isolate", action="store_true",
help="Try to run in such a way that multiple instances can run at "
"the same time. This may make it harder to debug a failure if it "
--- /dev/null
+#include "../../env/encoding.h"
+
+ .global main
+
+ .section .text
+main:
+ # MISA is only readable from machine mode
+ csrr t0, CSR_MISA
+ csrr t0, CSR_MISA
+ csrr t0, CSR_MISA
+ csrr t0, CSR_MISA
class Gdb(object):
def __init__(self,
- path=os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gdb")):
- self.child = pexpect.spawn(path)
+ cmd=os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gdb")):
+ self.child = pexpect.spawn(cmd)
self.child.logfile = file("gdb.log", "w")
- self.child.logfile.write("+ %s\n" % path)
+ self.child.logfile.write("+ %s\n" % cmd)
self.wait()
self.command("set confirm off")
self.command("set width 0")
src_dir := .
include $(src_dir)/rv64ui/Makefrag
+include $(src_dir)/rv64uc/Makefrag
include $(src_dir)/rv64um/Makefrag
include $(src_dir)/rv64ua/Makefrag
include $(src_dir)/rv64uf/Makefrag
include $(src_dir)/rv64si/Makefrag
include $(src_dir)/rv64mi/Makefrag
include $(src_dir)/rv32ui/Makefrag
+include $(src_dir)/rv32uc/Makefrag
include $(src_dir)/rv32um/Makefrag
include $(src_dir)/rv32ua/Makefrag
include $(src_dir)/rv32si/Makefrag
endef
$(eval $(call compile_template,rv32ui,-m32))
+$(eval $(call compile_template,rv32uc,-m32))
$(eval $(call compile_template,rv32um,-m32))
$(eval $(call compile_template,rv32ua,-m32))
$(eval $(call compile_template,rv32si,-m32))
$(eval $(call compile_template,rv32mi,-m32))
ifeq ($(XLEN),64)
$(eval $(call compile_template,rv64ui))
+$(eval $(call compile_template,rv64uc))
$(eval $(call compile_template,rv64um))
$(eval $(call compile_template,rv64ua))
$(eval $(call compile_template,rv64uf))
li x5, 2; \
bne x4, x5, 1b \
-#-----------------------------------------------------------------------
-# Test branch instructions
-#-----------------------------------------------------------------------
-
-#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x1, val1; \
- inst x1, 2f; \
- bne x0, TESTNUM, fail; \
-1: bne x0, TESTNUM, 3f; \
-2: inst x1, 1b; \
- bne x0, TESTNUM, fail; \
-3:
-
-#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x1, val1; \
- inst x1, 1f; \
- bne x0, TESTNUM, 2f; \
-1: bne x0, TESTNUM, fail; \
-2: inst x1, 1b; \
-3:
-
-#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x4, 0; \
-1: li x1, val1; \
- TEST_INSERT_NOPS_ ## nop_cycles \
- inst x1, fail; \
- addi x4, x4, 1; \
- li x5, 2; \
- bne x4, x5, 1b \
-
#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
#-----------------------------------------------------------------------
rv32mi_sc_tests = \
+ breakpoint \
csr \
+ mcsr \
illegal \
ma_fetch \
ma_addr \
- mcsr \
scall \
sbreak \
shamt \
--- /dev/null
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64mi/breakpoint.S"
--- /dev/null
+#=======================================================================
+# Makefrag for rv32uc tests
+#-----------------------------------------------------------------------
+
+rv32uc_sc_tests = \
+ rvc \
+
+rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
+rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
+
+spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uc/rvc.S"
csrr a1, tdrdata1
andi a1, a1, 0x7ff
bne a0, a1, 2f
+ .align 2
1:
# Trap handler should skip this instruction.
- j fail
+ beqz x0, fail
# Make sure reads don't trap.
li TESTNUM, 3
RVTEST_RV64M
RVTEST_CODE_BEGIN
- .align 3
.option norvc
- auipc s0, 0
+
+ la s0, data
# indicate it's a load test
li s1, CAUSE_MISALIGNED_LOAD
.data
RVTEST_DATA_BEGIN
+data:
+ .dword 0
+
TEST_DATA
RVTEST_DATA_END
--- /dev/null
+#=======================================================================
+# Makefrag for rv64uc tests
+#-----------------------------------------------------------------------
+
+rv64uc_sc_tests = \
+ rvc \
+
+rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests))
+rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests))
+
+spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rvc.S
+#-----------------------------------------------------------------------------
+#
+# Test RVC corner cases.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ .option push
+ .option norvc
+
+ #define RVC_TEST_CASE(n, r, v, code...) \
+ TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop)
+
+ // Make sure fetching a 4-byte instruction across a page boundary works.
+ li TESTNUM, 2
+ li a1, 666
+ li a2, 1
+ RVC_TEST_CASE (2, a1, 2, \
+ j 1f; \
+ .align 12; \
+ .skip 4094; \
+ 1: addi a1, a2, 1)
+
+ li sp, 0x1234
+ RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020)
+ RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496)
+ RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512)
+
+ la a1, data
+ RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1))
+#ifdef __riscv64
+ RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1))
+#endif
+
+ RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16)
+ RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16)
+#ifdef __riscv64
+ RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1)
+#endif
+
+ RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12)
+#ifdef __riscv64
+ RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#else
+ RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#endif
+ RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10)
+ RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0)
+ RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0)
+ RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0)
+ RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0)
+#ifdef __riscv64
+ RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0)
+ RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0)
+#endif
+ RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4)
+
+ RVC_TEST_CASE (30, ra, 0, \
+ li ra, 0; \
+ c.j 1f; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:)
+
+ RVC_TEST_CASE (31, x0, 0, \
+ li a0, 0; \
+ c.beqz a0, 1f; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:)
+
+ RVC_TEST_CASE (32, x0, 0, \
+ li a0, 1; \
+ c.bnez a0, 1f; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:)
+
+ RVC_TEST_CASE (33, x0, 0, \
+ li a0, 1; \
+ c.beqz a0, 1f; \
+ c.j 2f; \
+ 1:c.j fail; \
+ 2:)
+
+ RVC_TEST_CASE (34, x0, 0, \
+ li a0, 0; \
+ c.bnez a0, 1f; \
+ c.j 2f; \
+ 1:c.j fail; \
+ 2:)
+
+ RVC_TEST_CASE (35, ra, 0, \
+ la t0, 1f; \
+ li ra, 0; \
+ c.jr t0; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:)
+
+ RVC_TEST_CASE (36, ra, -2, \
+ la t0, 1f; \
+ li ra, 0; \
+ c.jalr t0; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:sub ra, ra, t0)
+
+#ifdef __riscv32
+ RVC_TEST_CASE (37, ra, -2, \
+ la t0, 1f; \
+ li ra, 0; \
+ c.jal 1f; \
+ c.j 2f; \
+ 1:c.j 1f; \
+ 2:j fail; \
+ 1:sub ra, ra, t0)
+#endif
+
+ la sp, data
+ RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp))
+#ifdef __riscv64
+ RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp))
+#endif
+
+ RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0)
+
+ .option pop
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+data:
+ .dword 0xfedcba9876543210
+ .dword 0xfedcba9876543210
+
+RVTEST_DATA_END