Test that superpage PTEs trap when PPN LSBs are set

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 50bdcfb0d07d8646f9874840f73b3cab0fdbf4d3..783522c1ed76ba7a3ce32fe408aa86891d5e1e2c 100644 (file)
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -55,6 +55,19 @@ RVTEST_CODE_BEGIN
   li a0, PTE_A | PTE_D
   and t0, t0, a0
   bne t0, a0, die
   li a0, PTE_A | PTE_D
   and t0, t0, a0
   bne t0, a0, die

+
+  # Enter MPRV again
+  li t0, MSTATUS_MPRV
+  csrs mstatus, t0
+
+  # Make sure that superpage entries trap when PPN LSBs are set.
+  li TESTNUM, 4
+  lw a0, page_table_1 - DRAM_BASE
+  or a0, a0, 1 << PTE_PPN_SHIFT
+  sw a0, page_table_1 - DRAM_BASE, t0
+  sfence.vma
+  sw a0, page_table_1 - DRAM_BASE, t0
+  j die

   
   RVTEST_PASS
 
   
   RVTEST_PASS
 


@@ -92,6 +105,11 @@ skip:
   sfence.vma
   mret
 
   sfence.vma
   mret
 

+1:
+  li t1, 4
+  bne TESTNUM, t1, 1f
+  j pass
+

 1:
 die:
   RVTEST_FAIL
 1:
 die:
   RVTEST_FAIL