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raw | patch | inline | side by side (parent: 57a2595)
By default debug=False
authorMegan Wachs <megan@sifive.com>
Mon, 8 Aug 2016 19:24:44 +0000 (12:24 -0700)
committerMegan Wachs <megan@sifive.com>
Mon, 8 Aug 2016 19:24:44 +0000 (12:24 -0700)
debug/gdbserver.py patch | blob | history

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 06935188e77e44427a4c1aa2176c5478d158f186..9d6f781b6b1fd7527942d7a0f1fefcc1dff18020 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -593,7 +593,7 @@ class FreedomE300SimTarget(Target):
     instruction_hardware_breakpoint_count = 2
        
     def server(self):
     instruction_hardware_breakpoint_count = 2
        
     def server(self):
-        sim = testlib.VcsSim(simv=parsed.run, debug=True)
+        sim = testlib.VcsSim(simv=parsed.run, debug=False)
         x = testlib.Openocd(cmd=parsed.cmd,
                             config="targets/%s/openocd.cfg" % self.name,
                             otherProcess = sim)
         x = testlib.Openocd(cmd=parsed.cmd,
                             config="targets/%s/openocd.cfg" % self.name,
                             otherProcess = sim)
@@ -610,7 +610,7 @@ class FreedomU500SimTarget(Target):
     instruction_hardware_breakpoint_count = 2
        
     def server(self):
     instruction_hardware_breakpoint_count = 2
        
     def server(self):
-        sim = testlib.VcsSim(simv=parsed.run, debug=True)
+        sim = testlib.VcsSim(simv=parsed.run, debug=False)
         x = testlib.Openocd(cmd=parsed.cmd,
                             config="targets/%s/openocd.cfg" % self.name,
                             otherProcess = sim)
         x = testlib.Openocd(cmd=parsed.cmd,
                             config="targets/%s/openocd.cfg" % self.name,
                             otherProcess = sim)