Move dirty bit test to rv64si directory

Not sure this is quite right, since the test technically runs in M-mode.

Also, remove unused rdnpc/example tests.

diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
index 4ae8733927ae679d009805b3d345702129196386..e4fa426d6a3d092973d807dd2d7b935a17373483 100644 (file)
--- a/isa/rv64mi/Makefrag
+++ b/isa/rv64mi/Makefrag
@@ -4,7 +4,6 @@
 
 rv64mi_sc_tests = \
        breakpoint \
 
 rv64mi_sc_tests = \
        breakpoint \

-       dirty \

        csr \
        mcsr \
        illegal \
        csr \
        mcsr \
        illegal \

diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
deleted file mode 100644 (file)
index 0314cf5..0000000
--- a/isa/rv64mi/dirty.S
+++ /dev/null
@@ -1,93 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# dirty.S
-#-----------------------------------------------------------------------------
-#
-# Test VM referenced and dirty bits.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64M
-RVTEST_CODE_BEGIN
-
-  # Turn on VM with superpage identity mapping
-  la a1, page_table_1
-  srl a1, a1, RISCV_PGSHIFT
-  la a2, page_table_2
-  srl a2, a2, RISCV_PGSHIFT
-  csrw sptbr, a1
-  sfence.vm
-  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
-  csrs mstatus, a1
-  la a1, 1f - DRAM_BASE
-  csrw mepc, a1
-  la a1, stvec_handler - DRAM_BASE
-  csrw stvec, a1
-  mret
-1:
-
-  # Try a faulting store to make sure dirty bit is not set
-  li TESTNUM, 2
-  li t0, 1
-  sw t0, dummy, t1
-
-  # Load new page table
-  li TESTNUM, 3
-  csrw sptbr, a2
-  sfence.vm
-
-  # Try a non-faulting store to make sure dirty bit is set
-  sw t0, dummy, t1
-
-  # Make sure R and D bits are set
-  lw t0, page_table_2
-  li t1, PTE_A | PTE_D
-  and t0, t0, t1
-  bne t0, t1, die
-  
-  RVTEST_PASS
-
-  TEST_PASSFAIL
-
-  .align 2
-stvec_handler:
-  csrr t0, scause
-  li t1, 2
-  bne TESTNUM, t1, 1f
-  # Make sure R bit is set
-  lw t0, page_table_1
-  li t1, PTE_A
-  and t0, t0, t1
-  bne t0, t1, die
-
-  # Make sure D bit is clear
-  lw t0, page_table_1
-  li t1, PTE_D
-  and t0, t0, t1
-  beq t0, t1, die
-
-  csrr t0, sepc
-  add t0, t0, 4
-  csrw sepc, t0
-  sret
-
-die:
-  RVTEST_FAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-.align 12
-page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
-dummy: .dword 0
-.align 12
-page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
-
-RVTEST_DATA_END

diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index 076ea5967d75c25b35c4658d25777c6c4e133293..c0dbce8f418d8a3125f62ab34bb301c830f2bcbb 100644 (file)
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -4,6 +4,7 @@
 
 rv64si_sc_tests = \
        csr \
 
 rv64si_sc_tests = \
        csr \

+       dirty \

        ma_fetch \
        scall \
        wfi \
        ma_fetch \
        scall \
        wfi \

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
new file mode 100644 (file)
index 0000000..0314cf5
--- /dev/null
+++ b/isa/rv64si/dirty.S
@@ -0,0 +1,93 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# dirty.S
+#-----------------------------------------------------------------------------
+#
+# Test VM referenced and dirty bits.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Turn on VM with superpage identity mapping
+  la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  la a2, page_table_2
+  srl a2, a2, RISCV_PGSHIFT
+  csrw sptbr, a1
+  sfence.vm
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
+  csrs mstatus, a1
+  la a1, 1f - DRAM_BASE
+  csrw mepc, a1
+  la a1, stvec_handler - DRAM_BASE
+  csrw stvec, a1
+  mret
+1:
+
+  # Try a faulting store to make sure dirty bit is not set
+  li TESTNUM, 2
+  li t0, 1
+  sw t0, dummy, t1
+
+  # Load new page table
+  li TESTNUM, 3
+  csrw sptbr, a2
+  sfence.vm
+
+  # Try a non-faulting store to make sure dirty bit is set
+  sw t0, dummy, t1
+
+  # Make sure R and D bits are set
+  lw t0, page_table_2
+  li t1, PTE_A | PTE_D
+  and t0, t0, t1
+  bne t0, t1, die
+  
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+stvec_handler:
+  csrr t0, scause
+  li t1, 2
+  bne TESTNUM, t1, 1f
+  # Make sure R bit is set
+  lw t0, page_table_1
+  li t1, PTE_A
+  and t0, t0, t1
+  bne t0, t1, die
+
+  # Make sure D bit is clear
+  lw t0, page_table_1
+  li t1, PTE_D
+  and t0, t0, t1
+  beq t0, t1, die
+
+  csrr t0, sepc
+  add t0, t0, 4
+  csrw sepc, t0
+  sret
+
+die:
+  RVTEST_FAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
+dummy: .dword 0
+.align 12
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
+
+RVTEST_DATA_END

diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index aeeb560794361998dc29b820b4b2f08fbb38c2b4..1867ea531398049dd3e24ce629338cb70c1245b6 100644 (file)
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -7,7 +7,7 @@ rv64ui_sc_tests = \
        and andi \
        auipc \
        beq bge bgeu blt bltu bne \
        and andi \
        auipc \
        beq bge bgeu blt bltu bne \

-       example simple \
+       simple \

        fence_i \
        jal jalr \
        lb lbu lh lhu lw lwu ld \
        fence_i \
        jal jalr \
        lb lbu lh lhu lw lwu ld \

diff --git a/isa/rv64ui/example.S b/isa/rv64ui/example.S
deleted file mode 100644 (file)
index 6c45fbd..0000000
--- a/isa/rv64ui/example.S
+++ /dev/null
@@ -1,27 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# simple.S
-#-----------------------------------------------------------------------------
-#
-# This is the most basic self checking test. If your simulator does not
-# pass thiss then there is little chance that it will pass any of the
-# more complicated self checking tests.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
-RVTEST_PASS
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END

diff --git a/isa/rv64ui/rdnpc.S b/isa/rv64ui/rdnpc.S
deleted file mode 100644 (file)
index e00839e..0000000
--- a/isa/rv64ui/rdnpc.S
+++ /dev/null
@@ -1,31 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# rdnpc_w.S
-#-----------------------------------------------------------------------------
-#
-# Test rdnpc instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a0, 4, \
-    rdnpc a0; \
-    jal 1f; \
-    1: sub a0, ra, a0; \
-  )
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END