revamp vector tests with new privileged spec, and add scalar pt tests

diff --git a/env b/env
index 4ea6feac5fe663fe82de53632883ced6205f57f8..be6511639c2d9291e9050682c4d7ce3e7042d061 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 4ea6feac5fe663fe82de53632883ced6205f57f8
+Subproject commit be6511639c2d9291e9050682c4d7ce3e7042d061

diff --git a/isa/Makefile b/isa/Makefile
index 9c7f37e468b3e6a4ec4cabcc5fa516b86e80de7a..4c8481500e6b2860aff800d15c44590a2abc75b6 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -6,9 +6,9 @@ isa_src_dir := .
 
 include $(isa_src_dir)/rv64ui/Makefrag
 include $(isa_src_dir)/rv64uf/Makefrag
-#include $(isa_src_dir)/rv64uv/Makefrag
+include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
-#include $(isa_src_dir)/rv64sv/Makefrag
+include $(isa_src_dir)/rv64sv/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
 include $(isa_src_dir)/rv32si/Makefrag
 
@@ -45,7 +45,7 @@ $$($(1)_p_tests): $(1)-p-%: $(1)/%.S
 $(1)_tests += $$($(1)_p_tests)
 
 $$($(1)_pt_tests): $(1)-pt-%: $(1)/%.S
-       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_pt_tests)
 
 $$($(1)_pm_tests): $(1)-pm-%: $(1)/%.S

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index 81052a6b4f2643eeb45e018991b85940fde31777..b4d0d78fdb929f5d52f9729a5f10526cc9481d14 100644 (file)
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -570,9 +570,8 @@ test_ ## testnum: \
 #-----------------------------------------------------------------------
 
 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
-  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  csrw evec, a0; \
+  csrw stvec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \
@@ -631,9 +630,8 @@ handler ## testnum: \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
-  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  csrw evec, a0; \
+  csrw stvec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \

diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 942f8f7c9aff83dc81a03508a899f5c57969c232..9d90b929a778970fb63baeb260c75f6ea712e8df 100644 (file)
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -3,7 +3,7 @@
 #-----------------------------------------------------------------------
 
 rv32ui_sc_tests = \
-   simple \
+       simple \
        add addi \
        amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
        and andi \
@@ -29,6 +29,7 @@ rv32ui_mc_tests = \
        lrsc
 
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
+rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
 rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
 
-spike_tests += $(rv32ui_p_tests) $(rv32ui_pm_tests)
+spike_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests)

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index e42dacda5e3aa83f998590d283275ea1f9cee212..a2c982744e16616f8b536d32522d9469133c6b67 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   li a0,33
   slli a0,a0,6

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index 2923d909aa466485f5b93cb2b9516b23245beab9..db077445aea213a709ac241601696885942e62ae 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   li a0,33
   vsetcfg a0

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index add9918b71f6d6c5ba637f6297dc1dd18b22630a..ae46fe0eda7c2e9773b9d3b40e33a6e4b35ae922 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   .word 0xff00002b
 

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index 7ca7fbac16f4c3068c2067c116f562620f5708f9..a2090ac51ff17b68e3708e50a7612a04421a897d 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -10,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA
-  csrs status, a0
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
   TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
 

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index 235f52b0bf22e0cfa7ae4ae34e2880ff834f9d14..dd616970adef770f5715bbb2827e49e1e5fd7a2f 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 2c2a5e6ea9c292e71e6c766abdd6b7cc9cf325a6..24745dc62f99cd1f25bb0dfe0064fa432859b416 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -10,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA
-  csrs status, a0
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
   TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
   TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 3bd74370c98eed8026981c98401dae7161eed119..398396e3be52e41e7df1b606f6f8806aeee905b8 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index fbece59e82fac87c81fa1243bfe31bcc313932b8..1390b54d7074720b3eb0929f4a8d02ddfc8d24d4 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -10,19 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
-  li a0, SR_EA | SR_EI
-  csrs status, a0
 
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 77e5f04a7413ecf6ab4680c2c26ab6669abdf741..4276b6495887161623aa97c023147f7ca81c6597 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index ec76a865e0fb673fffdd901c2930d7874ac3106e..2271e8f6c8673415526015ab4a550837b165c56a 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 6a178257e9bebcaaabdca1c5c0e4a32c495700a9..25c23c512b49907b377550dacf5540a9397ae7a1 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 818c11f628e1ea6717ec099772399f9b9fd5c23c..b7b169efa1f19922197580026f8bdbf23f8f9c7f 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -10,24 +10,18 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
-  la a0, SR_U64
-  csrs status, a0
-  csrc status, SR_S
+  csrw stvec,a3 # set exception handler
+
+  li a3, SSTATUS_PS
+  csrc sstatus, a3
+  la t0, 1f
+  csrw sepc, t0
+  sret
+1:
 
 privileged_inst:
   vxcptcause a3 # privileged inst

diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag
index bf5cd33ab82c33be6f751427082e621c6ebcc31e..f9ed202bc89b13f8ff84f2e9e07f8948cf65e2ec 100644 (file)
--- a/isa/rv64uf/Makefrag
+++ b/isa/rv64uf/Makefrag
@@ -7,12 +7,13 @@ rv64uf_sc_tests = \
        ldst move structural \
 
 rv64uf_sc_vec_tests = \
-#      fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
+       fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
+rv64uf_pt_tests = $(addprefix rv64uf-pt-, $(rv64uf_sc_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
-#rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
-#rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
-#rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
 
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
+spike_tests += $(rv64uf_p_tests) $(rv64uf_pt_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)

diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index a0f974ddc8d8f74aad4af8cbc1612ea204ba6a53..53f9a7f23989c35b0208a2440b04164622c972a8 100644 (file)
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -30,23 +30,24 @@ rv64ui_mc_tests = \
        lrsc
 
 rv64ui_sc_vec_tests = \
-       #add addi addiw addw \
-       #and andi \
-       #lui \
-       #mul mulh mulhsu mulhu mulw \
-       #or ori \
-       #sll slli slliw sllw \
-       #slt slti sltiu sltu \
-       #sra srai sraiw sraw \
-       #srl srli srliw srlw \
-       #sub subw \
-       #xor xori \
+       add addi addiw addw \
+       and andi \
+       lui \
+       mul mulh mulhsu mulhu mulw \
+       or ori \
+       sll slli slliw sllw \
+       slt slti sltiu sltu \
+       sra srai sraiw sraw \
+       srl srli srliw srlw \
+       sub subw \
+       xor xori \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
+rv64ui_pt_tests = $(addprefix rv64ui-pt-, $(rv64ui_sc_tests))
 rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
 rv64ui_p_vec_tests = $(addprefix rv64ui-p-vec-, $(rv64ui_sc_vec_tests))
 rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
 rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
 
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_pt_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)

diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag
index b65d7c03556bc16234d83dddb393c899b3d391b5..856721b7d8d8c75b1ecdee2a00e82fe44967ad75 100644 (file)
--- a/isa/rv64uv/Makefrag
+++ b/isa/rv64uv/Makefrag
@@ -19,7 +19,6 @@ rv64uv_sc_tests = \
        fcvt fma fma_many \
        fmovn fmovz \
        vvadd_d vvadd_w vvadd_fd vvadd_fw \
-       vvadd_packed \
        vvmul_d \
 
 rv64uv_sc_vec_tests = \