From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 27 Mar 2017 21:26:09 +0000 (-0700)
Subject: Separate page faults from physical memory access exceptions
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=1b78e242657f80250292f39e1f41bad2b1ab9d6c;ds=sidebyside

Separate page faults from physical memory access exceptions
---

diff --git a/benchmarks/pmp/pmp.c b/benchmarks/pmp/pmp.c
index 07eed8b..055ec79 100644
--- a/benchmarks/pmp/pmp.c
+++ b/benchmarks/pmp/pmp.c
@@ -16,7 +16,7 @@ uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
   if (cause == CAUSE_ILLEGAL_INSTRUCTION)
     exit(0); // no PMP support
 
-  if (!trap_expected)
+  if (!trap_expected || cause != CAUSE_LOAD_ACCESS)
     exit(1);
   trap_expected = 0;
   return epc + insn_len(epc);
diff --git a/env b/env
index 3dc6405..47fef2b 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 3dc64058de56fbac3b793e20707739f0b985303c
+Subproject commit 47fef2b463a484f3dafe979ec4e646990460dece
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 06c9780..86e4656 100644
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -58,7 +58,7 @@ RVTEST_CODE_BEGIN
   .align 2
 stvec_handler:
   csrr t0, scause
-  add t0, t0, -CAUSE_FAULT_STORE
+  add t0, t0, -CAUSE_STORE_PAGE_FAULT
   bnez t0, die
 
   li t1, 2