From: Andrew Waterman Date: Tue, 30 Aug 2016 18:11:08 +0000 (-0700) Subject: Add missing RV32 slt[i]u tests X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=2a9cd2c6cc19863c781bcaa8b276de6e528fba8e Add missing RV32 slt[i]u tests Closes #12. --- diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag index 7c211f1..7903b15 100644 --- a/isa/rv32ui/Makefrag +++ b/isa/rv32ui/Makefrag @@ -15,7 +15,7 @@ rv32ui_sc_tests = \ or ori \ sb sh sw \ sll slli \ - slt slti \ + slt slti sltiu sltu \ sra srai \ srl srli \ sub \ diff --git a/isa/rv32ui/slt.S b/isa/rv32ui/slt.S index 3abf82b..64a3dd9 100644 --- a/isa/rv32ui/slt.S +++ b/isa/rv32ui/slt.S @@ -1,84 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# slt.S -#----------------------------------------------------------------------------- -# -# Test slt instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, slt, 0, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, slt, 0, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, slt, 1, 0x00000003, 0x00000007 ); - TEST_RR_OP( 5, slt, 0, 0x00000007, 0x00000003 ); - - TEST_RR_OP( 6, slt, 0, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 7, slt, 1, 0x80000000, 0x00000000 ); - TEST_RR_OP( 8, slt, 1, 0x80000000, 0xffff8000 ); - - TEST_RR_OP( 9, slt, 1, 0x00000000, 0x00007fff ); - TEST_RR_OP( 10, slt, 0, 0x7fffffff, 0x00000000 ); - TEST_RR_OP( 11, slt, 0, 0x7fffffff, 0x00007fff ); - - TEST_RR_OP( 12, slt, 1, 0x80000000, 0x00007fff ); - TEST_RR_OP( 13, slt, 0, 0x7fffffff, 0xffff8000 ); - - TEST_RR_OP( 14, slt, 0, 0x00000000, 0xffffffff ); - TEST_RR_OP( 15, slt, 1, 0xffffffff, 0x00000001 ); - TEST_RR_OP( 16, slt, 0, 0xffffffff, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); - TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); - TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); - TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); - TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); - - TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); - TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); - TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); - TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); - TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); - TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); - - TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); - TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); - TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); - TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); - TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); - TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); - - TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); - TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); - TEST_RR_ZEROSRC12( 37, slt, 0 ); - TEST_RR_ZERODEST( 38, slt, 16, 30 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/slt.S" diff --git a/isa/rv32ui/slti.S b/isa/rv32ui/slti.S index 730cbe2..7484505 100644 --- a/isa/rv32ui/slti.S +++ b/isa/rv32ui/slti.S @@ -1,70 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# slti.S -#----------------------------------------------------------------------------- -# -# Test slti instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, slti, 0, 0x00000000, 0x000 ); - TEST_IMM_OP( 3, slti, 0, 0x00000001, 0x001 ); - TEST_IMM_OP( 4, slti, 1, 0x00000003, 0x007 ); - TEST_IMM_OP( 5, slti, 0, 0x00000007, 0x003 ); - - TEST_IMM_OP( 6, slti, 0, 0x00000000, 0x800 ); - TEST_IMM_OP( 7, slti, 1, 0x80000000, 0x000 ); - TEST_IMM_OP( 8, slti, 1, 0x80000000, 0x800 ); - - TEST_IMM_OP( 9, slti, 1, 0x00000000, 0x7ff ); - TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 ); - TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff ); - - TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff ); - TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 ); - - TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff ); - TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 ); - TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); - TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); - TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); - - TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); - TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); - TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); - - TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); - TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/slti.S" diff --git a/isa/rv32ui/sltiu.S b/isa/rv32ui/sltiu.S new file mode 100644 index 0000000..4185f9b --- /dev/null +++ b/isa/rv32ui/sltiu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltiu.S" diff --git a/isa/rv32ui/sltu.S b/isa/rv32ui/sltu.S new file mode 100644 index 0000000..bd92b26 --- /dev/null +++ b/isa/rv32ui/sltu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltu.S"