From: Richard Xia Date: Tue, 18 Oct 2016 21:38:24 +0000 (-0700) Subject: Pull port number from VCS output and pass to OpenOCD. X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=2faa3c064a9ac4704976fc06c2ed9c0eda842438;hp=c5e29cf553799b0434e2635e3f42314af337a5b2 Pull port number from VCS output and pass to OpenOCD. --- diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg index e8edda4..0b80885 100644 --- a/debug/targets/freedom-e300-sim/openocd.cfg +++ b/debug/targets/freedom-e300-sim/openocd.cfg @@ -1,6 +1,7 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] +jtag_vpi_set_port $::env(JTAG_VPI_PORT) set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg index e8edda4..0b80885 100644 --- a/debug/targets/freedom-u500-sim/openocd.cfg +++ b/debug/targets/freedom-u500-sim/openocd.cfg @@ -1,6 +1,7 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] +jtag_vpi_set_port $::env(JTAG_VPI_PORT) set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 diff --git a/debug/testlib.py b/debug/testlib.py index 29fa170..308bf21 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -102,8 +102,11 @@ class VcsSim(object): line = listenfile.readline() if not line: time.sleep(1) - if "Listening on port 5555" in line: + match = re.match(r"^Listening on port (\d+)$", line) + if match: done = True + self.port = int(match.group(1)) + print "Using port %d for JTAG VPI" % self.port def __del__(self): try: @@ -137,11 +140,14 @@ class Openocd(object): # line, since they are executed in order. cmd[1:1] = ["--command", "gdb_port %d" % self.port] + env = os.environ.copy() + env['JTAG_VPI_PORT'] = str(otherProcess.port) + logfile = open(Openocd.logname, "w") logfile.write("+ %s\n" % " ".join(cmd)) logfile.flush() self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, - stdout=logfile, stderr=logfile) + stdout=logfile, stderr=logfile, env=env) # Wait for OpenOCD to have made it through riscv_examine(). When using # OpenOCD to communicate with a simulator this may take a long time,