From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 2 Feb 2017 07:17:17 +0000 (-0800)
Subject: Test FMIN/FMAX NaN behavior
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c

Test FMIN/FMAX NaN behavior

See https://github.com/riscv/riscv-isa-sim/issues/76
---

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index fb89d1e..006f419 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -374,6 +374,11 @@ test_ ## testnum: \
 # Tests floating-point instructions
 #-----------------------------------------------------------------------
 
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
   li  TESTNUM, testnum; \
diff --git a/isa/rv64ud/fmin.S b/isa/rv64ud/fmin.S
index 82641bc..64c4aac 100644
--- a/isa/rv64ud/fmin.S
+++ b/isa/rv64ud/fmin.S
@@ -31,6 +31,11 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP2_D(16,  fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
   TEST_FP_OP2_D(17,  fmax.d, 0,       -1.0,       -1.0,       -2.0 );
 
+  # FMIN(sNaN, x) = canonical NaN
+  TEST_FP_OP2_D(20,  fmax.d, 0x10, qNaN, sNaN, 0);
+  # FMIN(qNaN, qNaN) = canonical NaN
+  TEST_FP_OP2_D(21,  fmax.d, 0x00, qNaN, NaN, NaN);
+
   TEST_PASSFAIL
 
 RVTEST_CODE_END
diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S
index a2650e5..5bbbf3f 100644
--- a/isa/rv64uf/fmin.S
+++ b/isa/rv64uf/fmin.S
@@ -31,6 +31,11 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP2_S(16,  fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 );
   TEST_FP_OP2_S(17,  fmax.s, 0,       -1.0,       -1.0,       -2.0 );
 
+  # FMIN(sNaN, x) = canonical NaN
+  TEST_FP_OP2_S(20,  fmax.s, 0x10, qNaNf, sNaNf, 0);
+  # FMIN(qNaN, qNaN) = canonical NaN
+  TEST_FP_OP2_S(21,  fmax.s, 0x00, qNaNf, NaN, NaN);
+
   TEST_PASSFAIL
 
 RVTEST_CODE_END