From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Thu, 28 Aug 2014 10:52:17 +0000 (-0700)
Subject: Added "simple" test to rv32ui.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=3af71c779ae5f34c16c1133b972b99ee9c2338b5

Added "simple" test to rv32ui.
---

diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index d487463..942f8f7 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -3,6 +3,7 @@
 #-----------------------------------------------------------------------
 
 rv32ui_sc_tests = \
+   simple \
 	add addi \
 	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
 	and andi \
diff --git a/isa/rv32ui/simple.S b/isa/rv32ui/simple.S
new file mode 100644
index 0000000..c247ce0
--- /dev/null
+++ b/isa/rv32ui/simple.S
@@ -0,0 +1,25 @@
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END