From: Tim Newsome <tim@sifive.com>
Date: Tue, 19 Jul 2016 01:33:10 +0000 (-0700)
Subject: Add 32-bit support.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=519794c8e91d1362dca8add5077277cc9bdc1611;hp=713f6a3089ac8b656d0a18874782e26d3039b22e

Add 32-bit support.
---

diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S
index 2725b67..115ccb5 100644
--- a/debug/programs/mprv.S
+++ b/debug/programs/mprv.S
@@ -12,7 +12,11 @@ main:
 
         # update mstatus
         csrr    t1, CSR_MSTATUS
+#ifdef __riscv32
+        li      t0, (MSTATUS_MPRV | (VM_SV32 << 24))
+#else
         li      t0, (MSTATUS_MPRV | (VM_SV39 << 24))
+#endif
         #li      t0, ((VM_SV39 << 24))
         or      t1, t0, t1
         csrw    CSR_MSTATUS, t1
@@ -34,5 +38,9 @@ data:
 
         .balign 0x1000
 page_table:
-        .word   ((0x80000000 >> 2) | PTE_V | PTE_TYPE_URWX_SRWX)
+#ifdef __riscv32
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
+#else
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
         .word   0
+#endif