From: Megan Wachs <megan@sifive.com>
Date: Mon, 8 Aug 2016 18:34:32 +0000 (-0700)
Subject: Add U500 Target
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=57a2595e46680771d8341e68679592c291ea024c

Add U500 Target
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 84ef27f..0693518 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -599,13 +599,30 @@ class FreedomE300SimTarget(Target):
                             otherProcess = sim)
         time.sleep(20)
         return x
+
     
+class FreedomU500SimTarget(Target):
+    name = "freedom-u500-sim"
+    xlen = 64
+    timeout = 240
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+       
+    def server(self):
+        sim = testlib.VcsSim(simv=parsed.run, debug=True)
+        x = testlib.Openocd(cmd=parsed.cmd,
+                            config="targets/%s/openocd.cfg" % self.name,
+                            otherProcess = sim)
+        time.sleep(20)
+        return x
+
 targets = [
         Spike32Target,
         Spike64Target,
         FreedomE300Target,
-        FreedomE300SimTarget
-        ]
+        FreedomE300SimTarget,
+        FreedomU500SimTarget]
 
 def main():
     parser = argparse.ArgumentParser(
diff --git a/debug/targets/freedom-u500-sim/link.lds b/debug/targets/freedom-u500-sim/link.lds
new file mode 100755
index 0000000..1dbb99c
--- /dev/null
+++ b/debug/targets/freedom-u500-sim/link.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    _gp = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg
new file mode 100644
index 0000000..767d229
--- /dev/null
+++ b/debug/targets/freedom-u500-sim/openocd.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+source [find interface/jtag_vpi.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+#reset_config trst_and_srst separate
+# Stupid long so I can see the LEDs
+#adapter_nsrst_delay 2000
+#jtag_ntrst_delay 1000
+#
+init
+#reset
+
+halt