From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 4 Jan 2017 19:45:18 +0000 (-0800)
Subject: Specify Spike ISA explicitly
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=6a1a38d421fd3e24bdc179d58d33572636b903b2;ds=sidebyside

Specify Spike ISA explicitly
---

diff --git a/benchmarks/Makefile b/benchmarks/Makefile
index ce9d4f9..bc17927 100644
--- a/benchmarks/Makefile
+++ b/benchmarks/Makefile
@@ -55,7 +55,7 @@ RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
 RISCV_LINK_MT ?= $(RISCV_GCC) -T $(src_dir)/common/test-mt.ld
 RISCV_LINK_OPTS ?= -nostdlib -nostartfiles -ffast-math -lgcc
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
-RISCV_SIM ?= spike
+RISCV_SIM ?= spike --isa=rv$(XLEN)gc
 
 VPATH += $(addprefix $(src_dir)/, $(bmarks))
 VPATH += $(src_dir)/common
diff --git a/isa/Makefile b/isa/Makefile
index 1afa4d6..3ed1b60 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -43,10 +43,10 @@ vpath %.S $(src_dir)
 	$(RISCV_OBJDUMP) $< > $@
 
 %.out: %
-	$(RISCV_SIM) $< 2> $@
+	$(RISCV_SIM) --isa=rv64gc $< 2> $@
 
 %.out32: %
-	$(RISCV_SIM) --isa=RV32 $< 2> $@
+	$(RISCV_SIM) --isa=rv32gc $< 2> $@
 
 define compile_template