From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Thu, 13 Nov 2014 11:11:05 +0000 (-0800)
Subject: make rv32si fault load/store test stronger
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=726a546463d5674205f1e8905cc082c6c807e79b;ds=sidebyside

make rv32si fault load/store test stronger
---

diff --git a/isa/rv32si/fa_addr_zscale_8192.S b/isa/rv32si/fa_addr_zscale_8192.S
index 8bb110a..37b6edf 100644
--- a/isa/rv32si/fa_addr_zscale_8192.S
+++ b/isa/rv32si/fa_addr_zscale_8192.S
@@ -58,7 +58,11 @@ loop:
   li s0, 0xbad1dea0
   beq s1, x0, loop
 
-  j pass
+  li TESTNUM, 10
+  li s0, 0x1ffc
+  lw x0, 0(s0) // if an exception is taken, then would fail because evec is set to evec_store
+
+  j pass // this time it should pass
 
   TEST_PASSFAIL