From: Tim Newsome <tim@sifive.com>
Date: Wed, 22 Jun 2016 02:20:27 +0000 (-0700)
Subject: Test step over invalid instruction.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=7c9510e7a7e224ee3d51ebe736a58f81017a71a0

Test step over invalid instruction.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 030b6a1..f7d8d2e 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -302,10 +302,10 @@ class StepTest(DeleteServer):
 
     def test_step(self):
         main = self.gdb.p("$pc")
-        for expected in (4, 0xc, 0x10, 0x18, 0x14, 0x14):
+        for expected in (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c):
             self.gdb.stepi()
             pc = self.gdb.p("$pc")
-            self.assertEqual(pc - main, expected)
+            self.assertEqual("%x" % pc, "%x" % (expected + main))
 
 class RegsTest(DeleteServer):
     def setUp(self):
diff --git a/debug/programs/step.S b/debug/programs/step.S
index 49f82d6..6601548 100644
--- a/debug/programs/step.S
+++ b/debug/programs/step.S
@@ -3,15 +3,22 @@
         .global main
 
 main:
-        li      t0, 5                   // 0
-        beq     zero, zero, one         // 0x4
-        nop                             // 0x8
+        la      t0, trap_entry          // 0, 4
+        csrw    mtvec, t0               // 0x8
+
+        li      t0, 5                   // 0xc
+        beq     zero, zero, one         // 0x10
+        nop                             // 0x14
 one:
-        beq     zero, t0, one           // 0xc
-        jal     two                     // 0x10
+        beq     zero, t0, one           // 0x18
+        jal     two                     // 0x1c
 
 three:
-        j       three                   // 0x14
+        .word   0                       // 0x20
+        nop                             // 0x24
 
 two:
-        ret                             // 0x18
+        ret                             // 0x28
+
+trap_entry:
+        j       trap_entry              // 0x2c