From: Andrew Waterman Date: Mon, 25 Nov 2013 10:25:42 +0000 (-0800) Subject: Update benchmarks to new privileged ISA X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=b374fd10b2b36124bb6813211a7ec690e1fa8350 Update benchmarks to new privileged ISA --- diff --git a/benchmarks/Makefile b/benchmarks/Makefile index 9eb05cd..dee7b23 100644 --- a/benchmarks/Makefile +++ b/benchmarks/Makefile @@ -25,7 +25,7 @@ bmarks = \ dhrystone \ spmv \ mt-vvadd \ - mt-matmul \ + #mt-matmul \ #vec-vvadd \ #vec-cmplxmult \ #vec-matmul \ @@ -51,17 +51,16 @@ HOST_COMP = gcc $(HOST_OPTS) RISCV_GCC = riscv-gcc RISCV_GCC_OPTS = -Wa,-march=RVIMAFDXhwacha -std=gnu99 -O2 -nostdlib -nostartfiles -ffast-math -RISCV_LINK = riscv-gcc -T $(bmarkdir)/common/test.ld +RISCV_LINK = riscv-gcc -T $(bmarkdir)/common/test.ld $(incs) RISCV_LINK_MT = riscv-gcc -T $(bmarkdir)/common/test-mt.ld RISCV_LINK_OPTS = -lc -RISCV_LINK_SYSCALL = $(bmarkdir)/common/syscalls.c -lc RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data RISCV_SIM = spike VPATH += $(addprefix $(bmarkdir)/, $(bmarks)) VPATH += $(bmarkdir)/common -incs += -I$(bmarkdir)/common $(addprefix -I$(bmarkdir)/, $(bmarks)) +incs += -I../env -I$(bmarkdir)/common $(addprefix -I$(bmarkdir)/, $(bmarks)) objs := include $(patsubst %, $(bmarkdir)/%/bmark.mk, $(bmarks)) diff --git a/benchmarks/common/crt-mt.S b/benchmarks/common/crt-mt.S index 90cd755..6cedec0 100644 --- a/benchmarks/common/crt-mt.S +++ b/benchmarks/common/crt-mt.S @@ -1,4 +1,4 @@ -#include "pcr.h" +#include "encoding.h" .data .globl _heapend @@ -44,13 +44,12 @@ _start: li x30,0 li x31,0 - # enable fp - setpcr status, SR_EF - - # enable vec - setpcr t0, status, SR_EV + # enable fp and accelerator + li a0, SR_EF | SR_EA + csrs status, a0 ## if that didn't stick, we don't have an FPU, so don't initialize it + csrr t0, status and t0, t0, SR_EF beqz t0, 1f @@ -91,7 +90,7 @@ _start: # get core id and number of cores - mfpcr a0,hartid + csrr a0, hartid lw a1, 4(zero) slli a2, a0, 13 diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 563360a..ae8706b 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -1,4 +1,4 @@ -#include "pcr.h" +#include "encoding.h" .data .globl _heapend @@ -45,17 +45,16 @@ _start: li x31,0 #ifdef __riscv64 - setpcr status, SR_S64 - setpcr status, SR_U64 + li a0, SR_U64 | SR_S64 + csrs status, a0 #endif - # enable fp - setpcr status, SR_EF - - # enable vec - setpcr t0, status, SR_EV + # enable fp and accelerator + li a0, SR_EF | SR_EA + csrs status, a0 ## if that didn't stick, we don't have an FPU, so don't initialize it + csrr t0, status and t0, t0, SR_EF beqz t0, 1f @@ -96,27 +95,27 @@ _start: lui a0, %hi(trap_entry) add a0, a0, %lo(trap_entry) - mtpcr a0, evec + csrw evec, a0 lui a0, %hi(main) add a0, a0, %lo(main) - mtpcr a0, epc + csrw epc, a0 # only allow core 0 to proceed -1:mfpcr a0, hartid +1:csrr a0, hartid bnez a0, 1b la sp,stacktop # jmp to main as a user program - eret + sret 1:b 1b .align 4 .globl trap_entry trap_entry: # only check for SYS_exit, otherwise crash out li a3, 1337 # magic "bad things" happened error code - mfpcr a1, cause + csrr a1, cause li a2, 6 # syscall exception number bne a1, a2, exit_error handle_syscall: @@ -125,12 +124,12 @@ handle_syscall: li a1, 1 # successful exit code move a3, a0 bne a3, a1, exit_error - mtpcr a1, tohost # exit successfully (tohost == 1) + csrw tohost, a1 # exit successfully (tohost == 1) 1:b 1b exit_error: sll a3, a3, 1 or a3, a3, 1 - mtpcr a3, tohost + csrw tohost, a3 1:b 1b .bss diff --git a/benchmarks/common/pcr.h b/benchmarks/common/pcr.h deleted file mode 100644 index 8780cdd..0000000 --- a/benchmarks/common/pcr.h +++ /dev/null @@ -1,124 +0,0 @@ -// See LICENSE for license details. - -#ifndef _RISCV_PCR_H -#define _RISCV_PCR_H - -#define SR_S 0x00000001 -#define SR_PS 0x00000002 -#define SR_EI 0x00000004 -#define SR_PEI 0x00000008 -#define SR_EF 0x00000010 -#define SR_U64 0x00000020 -#define SR_S64 0x00000040 -#define SR_VM 0x00000080 -#define SR_EV 0x00000100 -#define SR_IM 0x00FF0000 -#define SR_IP 0xFF000000 -#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP) -#define SR_IM_SHIFT 16 -#define SR_IP_SHIFT 24 - -#define PCR_SUP0 0 -#define PCR_SUP1 1 -#define PCR_EPC 2 -#define PCR_BADVADDR 3 -#define PCR_PTBR 4 -#define PCR_ASID 5 -#define PCR_COUNT 6 -#define PCR_COMPARE 7 -#define PCR_EVEC 8 -#define PCR_CAUSE 9 -#define PCR_SR 10 -#define PCR_HARTID 11 -#define PCR_IMPL 12 -#define PCR_FATC 13 -#define PCR_SEND_IPI 14 -#define PCR_CLR_IPI 15 -#define PCR_VECBANK 18 -#define PCR_VECCFG 19 -#define PCR_RESET 29 -#define PCR_TOHOST 30 -#define PCR_FROMHOST 31 - -#define IRQ_COP 2 -#define IRQ_IPI 5 -#define IRQ_HOST 6 -#define IRQ_TIMER 7 - -#define IMPL_SPIKE 1 -#define IMPL_ROCKET 2 - -#define CAUSE_MISALIGNED_FETCH 0 -#define CAUSE_FAULT_FETCH 1 -#define CAUSE_ILLEGAL_INSTRUCTION 2 -#define CAUSE_PRIVILEGED_INSTRUCTION 3 -#define CAUSE_FP_DISABLED 4 -#define CAUSE_SYSCALL 6 -#define CAUSE_BREAKPOINT 7 -#define CAUSE_MISALIGNED_LOAD 8 -#define CAUSE_MISALIGNED_STORE 9 -#define CAUSE_FAULT_LOAD 10 -#define CAUSE_FAULT_STORE 11 -#define CAUSE_VECTOR_DISABLED 12 -#define CAUSE_VECTOR_BANK 13 - -#define CAUSE_VECTOR_MISALIGNED_FETCH 24 -#define CAUSE_VECTOR_FAULT_FETCH 25 -#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26 -#define CAUSE_VECTOR_ILLEGAL_COMMAND 27 -#define CAUSE_VECTOR_MISALIGNED_LOAD 28 -#define CAUSE_VECTOR_MISALIGNED_STORE 29 -#define CAUSE_VECTOR_FAULT_LOAD 30 -#define CAUSE_VECTOR_FAULT_STORE 31 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Entry is a page Table descriptor -#define PTE_T 0x002 // Entry is a page Table, not a terminal node -#define PTE_G 0x004 // Global -#define PTE_UR 0x008 // User Write permission -#define PTE_UW 0x010 // User Read permission -#define PTE_UX 0x020 // User eXecute permission -#define PTE_SR 0x040 // Supervisor Read permission -#define PTE_SW 0x080 // Supervisor Write permission -#define PTE_SX 0x100 // Supervisor eXecute permission -#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) - -#ifdef __riscv - -#ifdef __riscv64 -# define RISCV_PGLEVELS 3 -# define RISCV_PGSHIFT 13 -#else -# define RISCV_PGLEVELS 2 -# define RISCV_PGSHIFT 12 -#endif -#define RISCV_PGLEVEL_BITS 10 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \ - asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \ - __tmp2; }) - -#define mfpcr(reg) ({ long __tmp; \ - asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \ - __tmp; }) - -#define setpcr(reg,val) ({ long __tmp; \ - asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#define clearpcr(reg,val) ({ long __tmp; \ - asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#define rdcycle() ({ unsigned long __tmp; \ - asm volatile ("rdcycle %0" : "=r"(__tmp)); \ - __tmp; }) - -#endif - -#endif - -#endif diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c index 0c1bc7f..4154ba4 100644 --- a/benchmarks/common/syscalls.c +++ b/benchmarks/common/syscalls.c @@ -2,7 +2,7 @@ #include #include #include -#include "pcr.h" +#include "encoding.h" void exit(int code) { @@ -10,7 +10,7 @@ void exit(int code) magic_mem[0] = SYS_exit; magic_mem[1] = code; __sync_synchronize(); - mtpcr(PCR_TOHOST, (long)magic_mem); + write_csr(tohost, (long)magic_mem); while(1); } @@ -22,8 +22,8 @@ void printstr(const char* s) magic_mem[2] = (unsigned long)s; magic_mem[3] = strlen(s); __sync_synchronize(); - mtpcr(PCR_TOHOST, (long)magic_mem); - while(mtpcr(PCR_FROMHOST, 0) == 0); + write_csr(tohost, (long)magic_mem); + while (swap_csr(fromhost, 0) == 0); } int putchar(int ch) @@ -42,8 +42,8 @@ int putchar(int ch) magic_mem[2] = (long)buf; magic_mem[3] = buflen; __sync_synchronize(); - mtpcr(PCR_TOHOST, (long)magic_mem); - while(mtpcr(PCR_FROMHOST, 0) == 0); + write_csr(tohost, (long)magic_mem); + while (swap_csr(fromhost, 0) == 0); buflen = 0; } diff --git a/benchmarks/common/util.h b/benchmarks/common/util.h index 79d9256..10f3169 100644 --- a/benchmarks/common/util.h +++ b/benchmarks/common/util.h @@ -51,7 +51,7 @@ void finishTest(int test_result) "li a2,0 ;" "li a3,0 ;" "li v0,%1 ;" - "syscall" : : "r"(test_result) , "i"(SYS_exit)); + "scall" : : "r"(test_result) , "i"(SYS_exit)); } #endif } diff --git a/benchmarks/mt-matmul/bmark.mk b/benchmarks/mt-matmul/bmark.mk index 67d6af3..7749951 100644 --- a/benchmarks/mt-matmul/bmark.mk +++ b/benchmarks/mt-matmul/bmark.mk @@ -23,7 +23,7 @@ $(mt_matmul_host_bin) : $(mt_matmul_c_src) mt_matmul_riscv_bin = mt-matmul.riscv $(mt_matmul_riscv_bin) : $(mt_matmul_c_objs) $(mt_matmul_riscv_objs) - $(RISCV_LINK_MT) $(RISCV_LINK_SYSCALL) $(mt_matmul_c_objs) $(mt_matmul_riscv_objs) -o $(mt_matmul_riscv_bin) + $(RISCV_LINK_MT) $(mt_matmul_c_objs) $(mt_matmul_riscv_objs) $(RISCV_LINK_OPTS) -o $(mt_matmul_riscv_bin) junk += $(mt_matmul_c_objs) $(mt_matmul_riscv_objs) \ $(mt_matmul_host_bin) $(mt_matmul_riscv_bin) diff --git a/benchmarks/mt-vvadd/bmark.mk b/benchmarks/mt-vvadd/bmark.mk index 0ab2504..1f8b3ed 100644 --- a/benchmarks/mt-vvadd/bmark.mk +++ b/benchmarks/mt-vvadd/bmark.mk @@ -10,6 +10,7 @@ mt_vvadd_c_src = \ mt-vvadd.c \ + syscalls.c \ mt_vvadd_riscv_src = \ crt-mt.S \ @@ -23,7 +24,7 @@ $(mt_vvadd_host_bin) : $(mt_vvadd_c_src) mt_vvadd_riscv_bin = mt-vvadd.riscv $(mt_vvadd_riscv_bin) : $(mt_vvadd_c_objs) $(mt_vvadd_riscv_objs) - $(RISCV_LINK_MT) $(RISCV_LINK_SYSCALL) $(mt_vvadd_c_objs) $(mt_vvadd_riscv_objs) -o $(mt_vvadd_riscv_bin) + $(RISCV_LINK_MT) $(mt_vvadd_c_objs) $(mt_vvadd_riscv_objs) $(RISCV_LINK_OPTS) -o $(mt_vvadd_riscv_bin) junk += $(mt_vvadd_c_objs) $(mt_vvadd_riscv_objs) \ $(mt_vvadd_host_bin) $(mt_vvadd_riscv_bin) diff --git a/env b/env index 9c4e083..75d8f53 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 9c4e0839779f302720173ad063fa25366cef21f7 +Subproject commit 75d8f53ef210c29495410503529db2ae5c73964d