From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Thu, 7 Aug 2014 00:26:58 +0000 (-0700)
Subject: updates
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=b6bcab870b1eaf0ed7b75e5458f9880510d26100

updates
---

diff --git a/README.md b/README.md
index 9a4e913..67dd772 100644
--- a/README.md
+++ b/README.md
@@ -134,7 +134,7 @@ registers (pc, x0-x31, f0-f31, fsr) can be accessed.
 The `rv32ui` and `rv64ui` TVMs are integer-only subsets of `rv32u` and `rv64u`
 respectively. These subsets can not use any floating-point instructions (major
 opcodes: LOAD-FP, STORE-FP, MADD, MSUB, NMSUB, NMADD, OP-FP), and hence cannot
-access the floating-point register state (f0â-f31 and fsr). The integer-only
+access the floating-point register state (f0-f31 and fsr). The integer-only
 TVMs are useful for initial processor bringup and to test simpler
 implementations that lack a hardware FPU.