From: Andrew Waterman Date: Sat, 21 Mar 2015 06:14:10 +0000 (-0700) Subject: Merge rv64si and rv32si tests X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=c3378e8d37d38432947451ab26a93bb5ae7eb3a1;hp=74bc584aa5be5d52ded54e44dbf465f63b03a629 Merge rv64si and rv32si tests --- diff --git a/isa/rv32si/csr.S b/isa/rv32si/csr.S index 9f095c7..3c414c0 100644 --- a/isa/rv32si/csr.S +++ b/isa/rv32si/csr.S @@ -1,15 +1,6 @@ # See LICENSE for license details. -#***************************************************************************** -# csr.S -#----------------------------------------------------------------------------- -# -# Test CSRRx and CSRRxI instructions. -# - #include "riscv_test.h" -#include "test_macros.h" - #undef RVTEST_RV64S #define RVTEST_RV64S RVTEST_RV32S diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S index 3bec030..ad5c3b1 100644 --- a/isa/rv32si/illegal.S +++ b/isa/rv32si/illegal.S @@ -1,43 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# illegal.S -#----------------------------------------------------------------------------- -# -# Test illegal instruction trap. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la t0, stvec - csrw stvec, t0 - - li TESTNUM, 2 - .word 0 - j fail - - j pass - - TEST_PASSFAIL - -stvec: - li t1, CAUSE_ILLEGAL_INSTRUCTION - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S -RVTEST_DATA_END +#include "../rv64si/illegal.S" diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S index 81c33f6..7e11423 100644 --- a/isa/rv32si/ipi.S +++ b/isa/rv32si/ipi.S @@ -1,15 +1,6 @@ # See LICENSE for license details. -#***************************************************************************** -# ipi.S -#----------------------------------------------------------------------------- -# -# Test interprocessor interrupts. -# - #include "riscv_test.h" -#include "test_macros.h" - #undef RVTEST_RV64S #define RVTEST_RV64S RVTEST_RV32S diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S index 13ac778..51465a2 100644 --- a/isa/rv32si/ma_addr.S +++ b/isa/rv32si/ma_addr.S @@ -1,89 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# ma_addr.S -#----------------------------------------------------------------------------- -# -# Test misaligned ld/st trap. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la s0, stvec_load - - la t0, stvec_load - csrw stvec, t0 - - li TESTNUM, 2 - lw x0, 1(s0) - j fail - - li TESTNUM, 3 - lw x0, 2(s0) - j fail - - li TESTNUM, 4 - lw x0, 3(s0) - j fail - - li TESTNUM, 5 - lh x0, 1(s0) - j fail - - li TESTNUM, 6 - lhu x0, 1(s0) - j fail - - la t0, stvec_store - csrw stvec, t0 - - li TESTNUM, 7 - sw x0, 1(s0) - j fail - - li TESTNUM, 8 - sw x0, 2(s0) - j fail - - li TESTNUM, 9 - sw x0, 3(s0) - j fail - - li TESTNUM, 10 - sh x0, 1(s0) - j fail - - j pass - - TEST_PASSFAIL - -stvec_load: - li t1, CAUSE_MISALIGNED_LOAD - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -stvec_store: - li t1, CAUSE_MISALIGNED_STORE - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S -RVTEST_DATA_END +#include "../rv64si/ma_addr.S" diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S index 4aa7973..2e5254f 100644 --- a/isa/rv32si/ma_fetch.S +++ b/isa/rv32si/ma_fetch.S @@ -1,61 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# ma_fetch.S -#----------------------------------------------------------------------------- -# -# Test misaligned fetch trap. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la t0, stvec - csrw stvec, t0 - - li TESTNUM, 2 - la t0, 1f - jr t0, 2 -1: - j fail - - li TESTNUM, 3 - la t0, 2f - jr t0, 1 -2: - // this test should pass, since the low bit should be masked off - - li TESTNUM, 4 - la t0, 3f - jr t0, 3 -3: - j fail - - j pass - - TEST_PASSFAIL - -stvec: - li t0, 3 - beq TESTNUM, t0, fail - - li t1, CAUSE_MISALIGNED_FETCH - csrr t0, scause - bne t0, t1, fail - li t1, 0 - csrr t0, sepc - addi t0, t0, 2 // skip over instruction after jalr - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S -RVTEST_DATA_END +#include "../rv64si/ma_fetch.S" diff --git a/isa/rv32si/sbreak.S b/isa/rv32si/sbreak.S index cd920db..3dcfba2 100644 --- a/isa/rv32si/sbreak.S +++ b/isa/rv32si/sbreak.S @@ -1,43 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# scall.S -#----------------------------------------------------------------------------- -# -# Test syscall trap. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la t0, stvec - csrw stvec, t0 - - li TESTNUM, 2 - sbreak - j fail - - j pass - - TEST_PASSFAIL - -stvec: - li t1, CAUSE_BREAKPOINT - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S -RVTEST_DATA_END +#include "../rv64si/sbreak.S" diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S index a036aaf..5b732c8 100644 --- a/isa/rv32si/scall.S +++ b/isa/rv32si/scall.S @@ -1,43 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# scall.S -#----------------------------------------------------------------------------- -# -# Test syscall trap. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32S -RVTEST_CODE_BEGIN - - la t0, stvec - csrw stvec, t0 - - li TESTNUM, 2 - scall - j fail - - j pass - - TEST_PASSFAIL - -stvec: - li t1, CAUSE_ECALL - csrr t0, scause - bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S -RVTEST_DATA_END +#include "../rv64si/scall.S" diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S index 5c627d5..a6847aa 100644 --- a/isa/rv32si/timer.S +++ b/isa/rv32si/timer.S @@ -1,15 +1,6 @@ # See LICENSE for license details. -#***************************************************************************** -# timer.S -#----------------------------------------------------------------------------- -# -# Test timer interrupt. -# - #include "riscv_test.h" -#include "test_macros.h" - #undef RVTEST_RV64S #define RVTEST_RV64S RVTEST_RV32S diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index 87982c6..802fc55 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -4,6 +4,11 @@ rv64si_sc_tests = \ csr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ timer \ dirty \ diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S new file mode 100644 index 0000000..b068118 --- /dev/null +++ b/isa/rv64si/illegal.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + .word 0 + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S new file mode 100644 index 0000000..19abe96 --- /dev/null +++ b/isa/rv64si/ma_addr.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la s0, stvec_load + + la t0, stvec_load + csrw stvec, t0 + +#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ + li TESTNUM, testnum; \ + insn x0, offset(base); \ + j fail \ + + MISALIGNED_LDST_TEST(2, lh, s0, 1) + MISALIGNED_LDST_TEST(3, lhu, s0, 1) + MISALIGNED_LDST_TEST(4, lw, s0, 1) + MISALIGNED_LDST_TEST(5, lw, s0, 2) + MISALIGNED_LDST_TEST(6, lw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(7, lwu, s0, 1) + MISALIGNED_LDST_TEST(8, lwu, s0, 2) + MISALIGNED_LDST_TEST(9, lwu, s0, 3) + + MISALIGNED_LDST_TEST(10, ld, s0, 1) + MISALIGNED_LDST_TEST(11, ld, s0, 2) + MISALIGNED_LDST_TEST(12, ld, s0, 3) + MISALIGNED_LDST_TEST(13, ld, s0, 4) + MISALIGNED_LDST_TEST(14, ld, s0, 5) + MISALIGNED_LDST_TEST(15, ld, s0, 6) + MISALIGNED_LDST_TEST(16, ld, s0, 7) +#endif + + la t0, stvec_store + csrw stvec, t0 + + MISALIGNED_LDST_TEST(22, sh, s0, 1) + MISALIGNED_LDST_TEST(23, sw, s0, 1) + MISALIGNED_LDST_TEST(24, sw, s0, 2) + MISALIGNED_LDST_TEST(25, sw, s0, 3) + +#ifdef __riscv64 + MISALIGNED_LDST_TEST(26, sd, s0, 1) + MISALIGNED_LDST_TEST(27, sd, s0, 2) + MISALIGNED_LDST_TEST(28, sd, s0, 3) + MISALIGNED_LDST_TEST(29, sd, s0, 4) + MISALIGNED_LDST_TEST(30, sd, s0, 5) + MISALIGNED_LDST_TEST(31, sd, s0, 6) + MISALIGNED_LDST_TEST(32, sd, s0, 7) +#endif + + TEST_PASSFAIL + + .align 3 +stvec_load: + li t1, CAUSE_MISALIGNED_LOAD + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +stvec_store: + li t1, CAUSE_MISALIGNED_STORE + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S new file mode 100644 index 0000000..ae8377d --- /dev/null +++ b/isa/rv64si/ma_fetch.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_fetch.S +#----------------------------------------------------------------------------- +# +# Test misaligned fetch trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + +#ifndef __rvc + li TESTNUM, 2 + li t1, 0 + la t0, 1f + jalr t1, t0, 2 +1: + j fail +#endif + + // This test should pass, since JALR ignores the target LSB + li TESTNUM, 3 + la t0, 1f + jalr t1, t0, 1 +1: + j 1f + j fail +1: + +#ifndef __rvc + li TESTNUM, 4 + li t1, 0 + la t0, 3f + jr t0, 3 +3: + j fail +#endif + + j pass + + TEST_PASSFAIL + +stvec: + # tests 2 and 4 should trap + li a0, 2 + beq TESTNUM, a0, 1f + li a0, 4 + beq TESTNUM, a0, 1f + j fail +1: + + # verify that return address was not written + bnez t1, fail + + # verify trap cause + li a1, CAUSE_MISALIGNED_FETCH + csrr a0, scause + bne a0, a1, fail + + # verify that epc == &jalr (== t0 - 4) + csrr a1, sepc + addi t0, t0, -4 + bne t0, a1, fail + + addi a1, a1, 8 + csrw sepc, a1 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S new file mode 100644 index 0000000..dbdf7ae --- /dev/null +++ b/isa/rv64si/sbreak.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + sbreak + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_BREAKPOINT + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S new file mode 100644 index 0000000..aa543e9 --- /dev/null +++ b/isa/rv64si/scall.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + la t0, stvec + csrw stvec, t0 + + li TESTNUM, 2 + scall + j fail + + j pass + + TEST_PASSFAIL + +stvec: + li t1, CAUSE_ECALL + csrr t0, scause + bne t0, t1, fail + csrr t0, sepc + addi t0, t0, 8 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END