From: Andrew Waterman Date: Wed, 17 Aug 2016 07:37:17 +0000 (-0700) Subject: Improve AMO tests X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=c8c14a5c4f29655465296fd8e3b2371c6899f604 Improve AMO tests - avoid code duplication between RV32 and RV64 variants - make LR/SC do something interesting on uniprocessors - avoid requiring M extension --- diff --git a/env b/env index 29bff57..52947c5 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 29bff576b64b3dec9d22853625441a0c03ef60d1 +Subproject commit 52947c5489f868174e9251a98376274183e35b40 diff --git a/isa/rv32ua/amoswap_w.S b/isa/rv32ua/amoswap_w.S index a32ae74..722b7bc 100644 --- a/isa/rv32ua/amoswap_w.S +++ b/isa/rv32ua/amoswap_w.S @@ -1,65 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffff800, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 +#include "../rv64ua/amoswap_w.S" diff --git a/isa/rv32ua/amoxor_w.S b/isa/rv32ua/amoxor_w.S index d4b775f..1858d7e 100644 --- a/isa/rv32ua/amoxor_w.S +++ b/isa/rv32ua/amoxor_w.S @@ -1,65 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x7ffff800, \ - li a1, 0xc0000001; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 +#include "../rv64ua/amoxor_w.S" diff --git a/isa/rv32ua/lrsc.S b/isa/rv32ua/lrsc.S index 3a3d05a..695a5c8 100644 --- a/isa/rv32ua/lrsc.S +++ b/isa/rv32ua/lrsc.S @@ -1,84 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lrsr.S -#----------------------------------------------------------------------------- -# -# Test LR/SC instructions. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - -# get a unique core id -la a0, coreid -li a1, 1 -amoadd.w a2, a1, (a0) - -# for now, only run this on core 0 -1:li a3, 1 -bgeu a2, a3, 1b - -1: lw a1, (a0) -bltu a1, a3, 1b - -# make sure that sc without a reservation fails. -TEST_CASE( 2, a4, 1, \ - la a0, foo; \ - sc.w a4, x0, (a0); \ -) - -# make sure that sc with the wrong reservation fails. -# TODO is this actually mandatory behavior? -TEST_CASE( 3, a4, 1, \ - la a0, foo; \ - add a1, a0, 1024; \ - lr.w a1, (a1); \ - sc.w a4, a1, (a0); \ -) - -# have each core add its coreid to foo 1000 times -la a0, foo -li a1, 1000 -1: lr.w a4, (a0) -add a4, a4, a2 -sc.w a4, a4, (a0) -bnez a4, 1b -add a1, a1, -1 -bnez a1, 1b - -# wait for all cores to finish -la a0, barrier -li a1, 1 -amoadd.w x0, a1, (a0) -1: lw a1, (a0) -blt a1, a3, 1b -fence - -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ -) - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -coreid: .word 0 -barrier: .word 0 -foo: .word 0 -RVTEST_DATA_END +#include "../rv64ua/lrsc.S" diff --git a/isa/rv64ua/amoxor_w.S b/isa/rv64ua/amoxor_w.S index 2b92323..1b305dd 100644 --- a/isa/rv64ua/amoxor_w.S +++ b/isa/rv64ua/amoxor_w.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN li a0, 0xffffffff80000000; \ li a1, 0xfffffffffffff800; \ la a3, amo_operand; \ - sd a0, 0(a3); \ + sw a0, 0(a3); \ nop; nop; nop; nop; \ nop; nop; nop; nop; \ nop; nop; nop; nop; \ @@ -28,24 +28,24 @@ RVTEST_CODE_BEGIN amoxor.w a4, a1, 0(a3); \ ) - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ + TEST_CASE(4, a4, 0x7ffff800, \ li a1, 0xc0000001; \ li a4, 16384; \ add a5, a3, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ amoxor.w a4, a1, 0(a3); \ ) - TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) TEST_PASSFAIL diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index 9422739..11eb7de 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -40,9 +40,12 @@ TEST_CASE( 3, a4, 1, \ sc.w a4, a1, (a0); \ ) -# have each core add its coreid to foo 1000 times +#define LOG_ITERATIONS 10 + +# have each core add its coreid+1 to foo 1024 times la a0, foo -li a1, 1000 +li a1, 1<