projects / riscv-tests.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Move debug testing from all into debug-check target.
[riscv-tests.git] / benchmarks / dhrystone /
2016-07-08 Andrew WatermanDon't use FPU in benchmarks that don't need to use... tree | commitdiff
2016-03-15 Andrew WatermanRework benchmarks to run in M-mode tree | commitdiff
2016-03-01 Colin SchmidtMerge pull request #8 from riscv/sqrt-171 tree | commitdiff
2016-02-27 Palmer DabbeltMerge pull request #10 from riscv/travis-dev tree | commitdiff
2016-02-27 Colin Schmidtremove malloc declaration from dhrystone tree | commitdiff
2015-05-01 Andrew WatermanFix dhrystone timing code tree | commitdiff
2015-05-01 Andrew WatermanMake dhrystone report correct-ish numbers tree | commitdiff
2015-01-10 Andrew WatermanAdd LICENSE tree | commitdiff
2015-01-05 Andrew WatermanAvoid deprecated "b" pseudo-op; use "j" instead tree | commitdiff
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests tree | commitdiff
2014-02-06 Andrew WatermanClean up benchmarks; support uarch-specific counters tree | commitdiff
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests tree | commitdiff
2013-10-10 Christopher CelioBenchmarks now run in user-mode. tree | commitdiff
2013-08-24 Andrew WatermanReflect changes to ISA tree | commitdiff
2013-04-30 Yunsup Leebenchmarks initial commit tree | commitdiff