Make qsort benchmark more meaningful
[riscv-tests.git] / benchmarks /
2014-03-26 Andrew WatermanMake qsort benchmark more meaningful
2014-02-23 Eric LoveSort fixes: support for repeated trials.
2014-02-20 Eric LoveMerge commit '0661b47765081c710af3df66ec698aa58ff14d5d'
2014-02-20 Eric LoveAdded TAV sort benchmarks
2014-02-12 Andrew WatermanRun benchmarks in user mode
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-02-06 Andrew WatermanClean up benchmarks; support uarch-specific counters
2014-02-05 Quan NguyenAdd Stephen's vector FFT code
2014-02-01 Henry CookMinor Makefile improvements
2013-11-25 Andrew WatermanUpdate benchmarks to new privileged ISA
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Christopher CelioBenchmarks now run in user-mode.
2013-08-25 Andrew WatermanDon't build vector benchmarks for now
2013-08-24 Andrew WatermanReflect changes to ISA
2013-08-24 Sebastien MiroloMerge pull request #1 from smirolo/configure
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-24 Sebastien Mirolofeature: add autoconf
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-04-30 Yunsup Leeadd benchmarks gitignore
2013-04-30 Yunsup Leebenchmarks initial commit