bump env
[riscv-tests.git] / debug / targets /
2018-09-13 Tim NewsomeAssert if HiFive1 program is too large.
2018-09-03 Tim NewsomeMerge pull request #156 from riscv/PrivChange
2018-08-29 Tim NewsomeAdd test case for `riscv expose_custom`.
2018-04-27 Megan WachsMerge pull request #125 from riscv/debug-delete-sim
2018-04-19 Megan WachsDelete E300Sim.py
2018-04-02 Tim NewsomeUse `gdb_report_register_access_error enable`
2018-03-27 Tim NewsomeTest debug authentication.
2018-03-01 Tim NewsomeTest debugging with/without a program buffer
2018-03-01 Tim NewsomeEnsure an error when reading a non-existent CSR.
2018-02-07 Tim NewsomeLink scripts shouldn't be executable.
2017-12-27 Tim NewsomeTest FPRs that aren't XLEN in size.
2017-10-24 Tim NewsomeIncrease dual-core RV64 timeouts.
2017-10-04 Tim NewsomeMerge pull request #79 from riscv/multigdb
2017-09-29 Tim NewsomeFix tests to work in multi-gdb mode.
2017-09-21 Tim NewsomeAdd coverage for single-core non-rtos OpenOCD.
2017-09-20 Tim NewsomeAllow multiple reset vectors.
2017-09-12 Tim NewsomeMerge pull request #69 from riscv/multicore
2017-09-01 Tim NewsomeUse 32-bit link script for 32-bit target.
2017-08-28 Tim NewsomeThis file isn't ready yet.
2017-08-28 Tim NewsomeIncrease remotetimeout for spike targets.
2017-08-28 Tim NewsomeMake pylint happy.
2017-08-28 Tim NewsomeWIP multicore testing.
2017-08-28 Tim NewsomeMake the debug tests aware of multicore.
2017-08-10 Tim NewsomeGive these sim targets a chance of passing.
2017-06-27 Tim NewsomeMerge pull request #55 from riscv/debug
2017-06-27 Tim NewsomeMerge pull request #56 from riscv/config
2017-06-26 Tim NewsomeMove target definition into individual files.
2017-06-15 Tim NewsomeTest 64-bit addressing.
2017-06-09 Tim NewsomeAdd final echo to E300/U500 OpenOCD scripts
2017-06-09 Tim NewsomeMake HiFive1 testing (mostly) work again
2017-05-16 Palmer DabbeltMerge pull request #47 from riscv/debug-0.13
2017-05-16 Palmer DabbeltLink the infinate loop at 0x10000000
2017-05-16 Megan Wachsdebug: Update OpenOCD configs.
2017-05-16 Palmer DabbeltMerge pull request #48 from riscv/tests
2017-05-15 Palmer DabbeltDon't use the RTOS, and do "reset halt"
2017-05-15 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-18 Megan Wachsdebug: Don't halt out of reset. It's unrealistic. Use...
2017-04-18 Megan Wachsdebug: Use RTOS OpenOCD for Spike for now.
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/newprogram' into...
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-14 Megan Wachsdebug: checkpoint of trying to get simulation tests...
2017-04-14 Megan Wachsdebug: working with newprogram branch
2017-03-30 Palmer DabbeltChange the global pointer symbol to __global_pointer$
2017-03-03 Palmer DabbeltResurrect spike debug support
2017-02-17 Tim NewsomeAdd HiFive1 target.
2016-10-19 Tim NewsomeMerge pull request #34 from richardxia/use-port-randomi...
2016-10-18 Richard XiaPull port number from VCS output and pass to OpenOCD.
2016-10-03 Tim NewsomeAdd test for memory read from invalid address.
2016-08-12 Tim NewsomeMerge pull request #21 from sifive/add_freedom_sim_targets
2016-08-11 Megan WachsAdd FreedomU500 & incorporate feedback
2016-08-08 Megan WachsAdd U500 Target
2016-08-08 Megan WachsAdded FreedomE300 Simulator target
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300. (#19)
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300.
2016-07-20 Andrew WatermanMerge pull request #17 from timsifive/debug
2016-07-19 Tim NewsomeI think I've finally got malloc working right.
2016-07-19 Tim NewsomeIncrease TCK speed.
2016-07-19 Tim NewsomeBump up speed.
2016-07-19 Tim NewsomeUpdate IDCODE.
2016-07-19 Tim NewsomeAdd simple register tests.
2016-07-19 Tim NewsomeAdd block test.
2016-07-19 Tim NewsomeAll tests pass with spike now.
2016-07-19 Tim NewsomeMade some progress towards working with spike.
2016-07-19 Tim NewsomeWIP on debug testing.