projects / riscv-tests.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Disable TriggerDmode while spike is changed.
[riscv-tests.git] / debug / targets /
2016-08-12 Tim NewsomeMerge pull request #21 from sifive/add_freedom_sim_targets tree | commitdiff
2016-08-11 Megan WachsAdd FreedomU500 & incorporate feedback tree | commitdiff
2016-08-08 Megan WachsAdd U500 Target tree | commitdiff
2016-08-08 Megan WachsAdded FreedomE300 Simulator target tree | commitdiff
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300. (#19) tree | commitdiff
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300. tree | commitdiff
2016-07-20 Andrew WatermanMerge pull request #17 from timsifive/debug tree | commitdiff
2016-07-19 Tim NewsomeI think I've finally got malloc working right. tree | commitdiff
2016-07-19 Tim NewsomeIncrease TCK speed. tree | commitdiff
2016-07-19 Tim NewsomeBump up speed. tree | commitdiff
2016-07-19 Tim NewsomeUpdate IDCODE. tree | commitdiff
2016-07-19 Tim NewsomeAdd simple register tests. tree | commitdiff
2016-07-19 Tim NewsomeAdd block test. tree | commitdiff
2016-07-19 Tim NewsomeAll tests pass with spike now. tree | commitdiff
2016-07-19 Tim NewsomeMade some progress towards working with spike. tree | commitdiff
2016-07-19 Tim NewsomeWIP on debug testing. tree | commitdiff