Improve reg test a little.
[riscv-tests.git] / debug / targets /
2016-10-19 Tim NewsomeMerge pull request #34 from richardxia/use-port-randomi...
2016-10-18 Richard XiaPull port number from VCS output and pass to OpenOCD.
2016-10-03 Tim NewsomeAdd test for memory read from invalid address.
2016-08-12 Tim NewsomeMerge pull request #21 from sifive/add_freedom_sim_targets
2016-08-11 Megan WachsAdd FreedomU500 & incorporate feedback
2016-08-08 Megan WachsAdd U500 Target
2016-08-08 Megan WachsAdded FreedomE300 Simulator target
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300. (#19)
2016-07-27 Tim NewsomeRename m2gl_m2s to freedom-e300.
2016-07-20 Andrew WatermanMerge pull request #17 from timsifive/debug
2016-07-19 Tim NewsomeI think I've finally got malloc working right.
2016-07-19 Tim NewsomeIncrease TCK speed.
2016-07-19 Tim NewsomeBump up speed.
2016-07-19 Tim NewsomeUpdate IDCODE.
2016-07-19 Tim NewsomeAdd simple register tests.
2016-07-19 Tim NewsomeAdd block test.
2016-07-19 Tim NewsomeAll tests pass with spike now.
2016-07-19 Tim NewsomeMade some progress towards working with spike.
2016-07-19 Tim NewsomeWIP on debug testing.