skip user-mode trap tests in rv32mi/rv64mi-p-csr if no user mode
[riscv-tests.git] / isa / Makefile
2016-07-19 Andrew WatermanDefault to XLEN=64 when building in-place
2016-07-12 Palmer DabbeltAdd a "--with-xlen" configure argument (#16)
2016-06-22 Howard Maoseparate ua and um tests from ui tests
2016-06-22 Howard Maosplit up rv64uf and rv64ud isa tests
2016-05-03 Howard Maoget rid of empty asm test
2016-05-03 Howard Maoadd empty ISA test
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-14 Andrew WatermanMore RV32 tests
2016-03-03 Andrew WatermanUndo accidental Makefile modification
2016-03-03 Andrew WatermanWIP on priv spec v1.9
2016-03-03 Andrew WatermanFix ./configure in root
2016-03-01 Colin SchmidtMerge pull request #8 from riscv/sqrt-171
2016-02-29 Andrew WatermanFix capitalization of XLEN variable
2016-02-27 Palmer DabbeltMerge pull request #10 from riscv/travis-dev
2016-02-27 Colin Schmidtonly build the rv32 bit tests if xlen is 32
2016-02-27 Colin Schmidtallow make variables to be overwritten update configure
2015-12-04 Andrew WatermanMerge pull request #4 from pmundkur/devel
2015-09-21 Andrew WatermanRemove Hwacha v3 tests
2015-08-04 Andrew WatermanUse medany code model, not PIC, for ISA tests
2015-07-07 Andrew WatermanCoherence torture test for VM tests
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests
2015-03-16 Yunsup Leerevamp vector tests with new privileged spec, and add...
2015-03-13 Andrew WatermanUpdate to new privileged spec
2014-12-04 Andrew WatermanUse new toolchain and calling convention
2014-11-13 Yunsup Leeenable make subsets
2014-11-07 Andrew WatermanFix build with riscv-gcc version 4.9
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-02-11 Andrew WatermanRevert to old AUIPC definition
2014-02-01 Andrew WatermanShrink hex dumps
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2013-10-17 Yunsup Leeadd passing physical vector tests back in
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Yunsup Leerevamp hwacha tests
2013-09-21 Andrew WatermanRe-enable virtual memory tests
2013-08-25 Andrew Watermandon't emit vvcfg for now
2013-08-24 Andrew WatermanReflect changes to ISA
2013-08-24 Sebastien MiroloMerge pull request #1 from smirolo/configure
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-24 Sebastien Mirolofeature: add autoconf
2013-06-10 Andrew WatermanDon't disassemble zeros
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-04-30 Andrew Watermanadd first RV32 tests
2013-04-24 Yunsup Leecleanup Makefiles in isa