git.libre-soc.org Git - riscv-tests.git/history - isa/macros/vector/test

2017-01-04	Andrew Waterman	Remove Hwacha macros	commit \| commitdiff
2016-05-01	Andrew Waterman	ERET -> xRET; new memory map	commit \| commitdiff
2015-03-13	Andrew Waterman	Update to new privileged spec	commit \| commitdiff
2015-01-10	Andrew Waterman	Add LICENSE	commit \| commitdiff
2015-01-05	Andrew Waterman	Avoid deprecated "b" pseudo-op; use "j" instead	commit \| commitdiff
2014-03-18	Andrew Waterman	Check FP corner cases and flags	commit \| commitdiff
2014-02-11	Adam Izraelevitz	Merge branch 'master' of github.com:ucb-bar/riscv-tests	commit \| commitdiff
2014-01-31	Andrew Waterman	Reference TESTNUM instead of x28 directly	commit \| commitdiff
2013-11-24	Andrew Waterman	Update to new privileged ISA	commit \| commitdiff
2013-11-06	Yunsup Lee	correctly set SR_EA bit for all vector physical tests	commit \| commitdiff
2013-10-10	Christopher Celio	Merge branch 'master' of github.com:ucb-bar/riscv-tests	commit \| commitdiff
2013-10-10	Yunsup Lee	revamp hwacha tests	commit \| commitdiff
2013-08-24	Andrew Waterman	Reflect changes to ISA	commit \| commitdiff
2013-04-24	Yunsup Lee	add more header information to test_macros	commit \| commitdiff
2013-04-22	Yunsup Lee	initial commit	commit \| commitdiff