Pull port number from VCS output and pass to OpenOCD.
[riscv-tests.git] / isa / macros /
2016-10-10 Andrew WatermanAlign FP data sections
2016-08-12 Tim NewsomeMerge pull request #21 from sifive/add_freedom_sim_targets
2016-08-08 Colin Schmidtmove fclass macros into the same file as the rest ...
2016-08-08 Megan WachsMerge remote-tracking branch 'origin/master'
2016-07-29 Andrew WatermanAdd an RVC test
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-01-30 Andrew WatermanMerge pull request #7 from riscv/nan2
2016-01-29 Palmer DabbeltCheck NAN values in fdiv tests
2015-12-14 Howard Maochange la to li as appropriate in test macros
2015-12-04 Andrew WatermanMerge pull request #4 from pmundkur/devel
2015-09-21 Andrew WatermanRemove Hwacha v3 tests
2015-03-21 Andrew WatermanAdd fdiv test
2015-03-17 Yunsup Leerelay hwacha cause/aux to scause/sbadaddr
2015-03-16 Yunsup Leerevamp vector tests with new privileged spec, and add...
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-10 Andrew WatermanAdd LICENSE
2015-01-05 Andrew WatermanAvoid deprecated "b" pseudo-op; use "j" instead
2014-12-04 Andrew WatermanRely on assembler to relax far branches
2014-03-18 Andrew WatermanCheck FP corner cases and flags
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-01-31 Andrew WatermanReference TESTNUM instead of x28 directly
2013-11-24 Andrew WatermanUpdate to new privileged ISA
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical tests
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Yunsup Leerevamp hwacha tests
2013-08-24 Andrew WatermanReflect changes to ISA
2013-04-24 Yunsup Leeadd more header information to test_macros
2013-04-22 Yunsup Leeinitial commit