Verify that mtval/stval is written correctly on misaligned fetch
[riscv-tests.git] / isa / rv32mi /
2017-05-18 Megan WachsMerge pull request #52 from riscv/vcs_sim_cmd
2017-05-17 Andrew WatermanManually assemble bad shift amount, since assembler...
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-07 Andrew WatermanRemove defunct IPI tests
2016-08-08 Megan WachsMerge remote-tracking branch 'origin/master'
2016-07-29 Andrew WatermanAdd RV32 RVC and breakpoint tests
2016-07-22 Andrew WatermanMove rv32mi dirty bit test to rv32si
2016-07-08 Andrew WatermanUpdate WFI test for priv v1.9
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-10 Andrew WatermanAdd missing rv32mi/rv32si tests
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2015-07-05 Andrew WatermanNew M-mode timers
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests