Don't use stats register; refer to uarch counters by number
[riscv-tests.git] / isa / rv32mi /
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-10 Andrew WatermanAdd missing rv32mi/rv32si tests
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2015-07-05 Andrew WatermanNew M-mode timers
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests