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Add some immediate trigger tests.
[riscv-tests.git] / isa / rv32si /
2016-07-22 Andrew WatermanMove rv32mi dirty bit test to rv32si tree | commitdiff
2016-03-15 Andrew WatermanMerge branch 'priv-1.9' tree | commitdiff
2016-03-10 Andrew WatermanAdd missing rv32mi/rv32si tests tree | commitdiff
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode tree | commitdiff
2015-07-05 Andrew WatermanNew M-mode timers tree | commitdiff
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32 tree | commitdiff
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests tree | commitdiff
2015-03-21 Andrew WatermanMerge rv64si and rv32si tests tree | commitdiff
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret tree | commitdiff
2015-03-13 Andrew WatermanUpdate to new privileged spec tree | commitdiff
2015-02-19 Andrew WatermanUnify rv32/rv64 timer tests tree | commitdiff
2015-01-10 Andrew WatermanAdd LICENSE tree | commitdiff
2015-01-03 Andrew WatermanOn misaligned fetch, EPC = branch target, not source tree | commitdiff
2014-11-22 Yunsup Leerelax rv32si timer test a bit tree | commitdiff
2014-11-13 Yunsup Leeremove zscale specific tests tree | commitdiff
2014-11-13 Yunsup Leemake rv32si fault load/store test stronger tree | commitdiff
2014-11-13 Yunsup Leebeef up rv32si tests tree | commitdiff
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests tree | commitdiff
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5] tree | commitdiff