Remove deprecated uarch counters; support RVC for benchmarks
[riscv-tests.git] / isa / rv32ui /
2016-07-12 Andrew WatermanRemove instruction width assumptions to support RVC
2016-07-12 Andrew WatermanRemove vestigial j instruction test; improve jal test
2016-06-22 Howard Maoseparate ua and um tests from ui tests
2016-06-15 Sebastian Bøerv32ui: sh: Added side effect test (#14)
2016-05-23 Andrew WatermanEnable LR/SC tests, even for uniprocessors
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-14 Andrew WatermanMore RV32 tests
2016-03-03 Andrew WatermanMake JALR test sensible in RISC-V, rather than SMIPS
2016-03-01 Colin SchmidtMerge pull request #8 from riscv/sqrt-171
2016-02-29 Andrew WatermanStrip big-endian tests
2015-04-13 Andrew WatermanMerge pull request #3 from joerchan/master
2015-04-13 Joakim AnderssonCorrect expected high value of multiplication
2015-04-12 Joakim AnderssonBetter coverage of mul high instructions
2015-03-16 Yunsup Leerevamp vector tests with new privileged spec, and add...
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-10 Andrew WatermanAdd LICENSE
2014-11-07 Andrew WatermanDon't access memory outside of the binary's range
2014-08-28 Christopher CelioAdded "simple" test to rv32ui.
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-02-11 Andrew WatermanRevert to old AUIPC definition
2014-02-01 Andrew WatermanShrink hex dumps
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2014-01-31 Andrew WatermanReference TESTNUM instead of x28 directly
2014-01-24 Eric LoveDone with rv32ui asm test ports
2014-01-24 Eric LoveFixed srl, srli
2014-01-24 Eric Lovesrl and srai
2014-01-23 Eric LoveFirst round of rv32ui asm tests
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-26 Andrew WatermanRemove JALR static hints
2013-04-30 Andrew Watermanadd first RV32 tests