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[riscv-tests.git]
/
isa
/
rv64mi
/ dirty.S
2016-07-22
Andrew Waterman
Move dirty bit test to rv64si directory
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2016-07-12
Andrew Waterman
Remove instruction width assumptions to support RVC
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2016-07-06
Andrew Waterman
Update to new PTE format
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2016-05-02
Andrew Waterman
Stop using tohost/fromhost registers
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2016-05-01
Andrew Waterman
ERET -> xRET; new memory map
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2016-03-15
Andrew Waterman
Merge branch 'priv-1.9'
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2016-03-10
Andrew Waterman
Add missing rv32mi/rv32si tests
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2016-03-03
Andrew Waterman
WIP on priv spec v1.9
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2015-05-09
Andrew Waterman
Update to privileged architecture version 1.7
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2015-04-04
Andrew Waterman
Run RV32 tests on spike with --isa=RV32
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2015-03-27
Andrew Waterman
New virtual memory implementation (Sv39)
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2015-03-25
Yunsup Lee
split out S-mode tests and M-mode tests
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