git.libre-soc.org Git - riscv-tests.git/history

2016-07-12	Andrew Waterman	Remove instruction width assumptions to support RVC	blob \| commitdiff \| raw
2016-07-06	Andrew Waterman	Update to new PTE format	blob \| commitdiff \| raw \| diff to current
2016-05-02	Andrew Waterman	Stop using tohost/fromhost registers	blob \| commitdiff \| raw \| diff to current
2016-05-01	Andrew Waterman	ERET -> xRET; new memory map	blob \| commitdiff \| raw \| diff to current
2016-03-15	Andrew Waterman	Merge branch 'priv-1.9'	blob \| commitdiff \| raw \| diff to current
2016-03-10	Andrew Waterman	Add missing rv32mi/rv32si tests	blob \| commitdiff \| raw \| diff to current
2016-03-03	Andrew Waterman	WIP on priv spec v1.9	blob \| commitdiff \| raw \| diff to current
2015-05-09	Andrew Waterman	Update to privileged architecture version 1.7	blob \| commitdiff \| raw \| diff to current
2015-04-04	Andrew Waterman	Run RV32 tests on spike with --isa=RV32	blob \| commitdiff \| raw \| diff to current
2015-03-27	Andrew Waterman	New virtual memory implementation (Sv39)	blob \| commitdiff \| raw \| diff to current
2015-03-25	Yunsup Lee	split out S-mode tests and M-mode tests	blob \| commitdiff \| raw \| diff to current