Test mstatus.TW, mstatus.TVM, and mstatus.TSR features
[riscv-tests.git] / isa / rv64mi / illegal.S
2017-03-13 Andrew WatermanTest mstatus.TW, mstatus.TVM, and mstatus.TSR features
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests