Test more than one breakpoint at a time, if present
[riscv-tests.git] / isa / rv64mi /
2016-06-10 Andrew WatermanTest more than one breakpoint at a time, if present
2016-06-10 Andrew WatermanUpdate breakpoint spec
2016-06-09 Andrew WatermanDon't arm breakpoint before setting break address
2016-06-09 Andrew WatermanAdd HW breakpoint test
2016-05-02 Andrew WatermanRemove incorrect M-mode WFI test
2016-05-02 Andrew WatermanStop using tohost/fromhost registers
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-04-06 Andrew WatermanFix expected misa register value for RV32
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-10 Andrew WatermanAdd missing rv32mi/rv32si tests
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2016-03-03 Andrew WatermanWIP on priv spec v1.9
2016-01-13 Andrew WatermanWrite 1, not 0, to MIPI
2015-12-04 Andrew WatermanMerge pull request #4 from pmundkur/devel
2015-11-16 Andrew WatermanUpdate IPI test to work with new mechanism
2015-10-19 Andrew WatermanAvoid REMU in timer test
2015-07-05 Andrew WatermanNew M-mode timers
2015-05-19 Andrew WatermanAdd basic WFI test
2015-05-09 Andrew WatermanUpdate to privileged architecture version 1.7
2015-04-04 Andrew WatermanRun RV32 tests on spike with --isa=RV32
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests