Update to new breakpoint & counter spec
[riscv-tests.git] / isa / rv64si / csr.S
2016-08-27 Andrew WatermanUpdate to new breakpoint & counter spec
2016-07-22 Howard Maoskip user-mode trap tests in rv32mi/rv64mi-p-csr if...
2016-07-12 Andrew WatermanRemove instruction width assumptions to support RVC
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2016-03-03 Andrew WatermanWIP on priv spec v1.9
2015-05-09 Andrew WatermanUpdate to privileged architecture version 1.7
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-10 Andrew WatermanAdd LICENSE
2014-02-11 Adam IzraelevitzMerge branch 'master' of github.com:ucb-bar/riscv-tests
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2014-01-31 Andrew WatermanMake CSR test much more robust
2014-01-22 Andrew WatermanAdd CSRRx/CSRRxI test