git.libre-soc.org Git - riscv-tests.git/history

2018-03-21	Andrew Waterman	Make misa.C test conform to Hauser proposal	commit \| commitdiff
2018-02-27	Andrew Waterman	Add test for clearing misa.C while PC is misaligned...	commit \| commitdiff
2017-11-12	Andrew Waterman	Make sure that code is 4-byte aligned before disabling...	commit \| commitdiff
2017-10-30	Richard Xia	Declare trap handlers as global symbols. (#87)	commit \| commitdiff
2017-10-27	Andrew Waterman	Verify that mtval/stval is written correctly on misalig...	commit \| commitdiff
2017-09-12	Tim Newsome	Merge pull request #69 from riscv/multicore	commit \| commitdiff
2017-09-01	Andrew Waterman	Improve ma_fetch test to cover JAL and branches	commit \| commitdiff
2016-07-22	Andrew Waterman	Make ma_fetch test robust against code size changes	commit \| commitdiff
2016-07-12	Andrew Waterman	Remove instruction width assumptions to support RVC	commit \| commitdiff
2016-05-01	Andrew Waterman	ERET -> xRET; new memory map	commit \| commitdiff
2016-03-15	Andrew Waterman	Merge branch 'priv-1.9'	commit \| commitdiff
2016-03-03	Andrew Waterman	Fix ma_fetch to work with or without RVC	commit \| commitdiff
2015-03-25	Yunsup Lee	split out S-mode tests and M-mode tests	commit \| commitdiff
2015-03-21	Andrew Waterman	Merge rv64si and rv32si tests	commit \| commitdiff