git.libre-soc.org Git - riscv-tests.git/history

2018-08-22	Tim Newsome	Merge branch 'master' of https://github.com/riscv/riscv...	commit \| commitdiff
2018-08-21	Srivatsa Yogendra	Changing the register mstatus is read into (#152)	commit \| commitdiff
2018-08-21	Andrew Waterman	Revert "Fix to solve the failing tests shamt, csr and...	commit \| commitdiff
2018-08-18	Srivatsa Yogendra	Fix to solve the failing tests shamt, csr and scall...	commit \| commitdiff
2017-11-22	Christopher Celio	Check sepc for rv64si/scall test. (#107)	commit \| commitdiff
2017-11-10	Andrew Waterman	Make rv64mi-p-ecall work when U-mode is not present	commit \| commitdiff
2017-10-30	Richard Xia	Declare trap handlers as global symbols. (#87)	commit \| commitdiff
2016-07-12	Andrew Waterman	Remove instruction width assumptions to support RVC	commit \| commitdiff
2016-05-01	Andrew Waterman	ERET -> xRET; new memory map	commit \| commitdiff
2016-03-15	Andrew Waterman	Merge branch 'priv-1.9'	commit \| commitdiff
2016-03-03	Andrew Waterman	WIP on priv spec v1.9	commit \| commitdiff
2015-05-09	Andrew Waterman	Update to privileged architecture version 1.7	commit \| commitdiff
2015-03-25	Yunsup Lee	split out S-mode tests and M-mode tests	commit \| commitdiff
2015-03-21	Andrew Waterman	Merge rv64si and rv32si tests	commit \| commitdiff