Remove vestigial j instruction test; improve jal test
[riscv-tests.git] / isa / rv64si /
2016-07-08 Andrew WatermanUpdate WFI test for priv v1.9
2016-05-02 Andrew WatermanRemove incorrect M-mode WFI test
2016-05-01 Andrew WatermanERET -> xRET; new memory map
2016-03-15 Andrew WatermanMerge branch 'priv-1.9'
2016-03-03 Andrew WatermanMake WFI test more strict
2016-03-03 Andrew WatermanSome S-mode tests really only belong in M-mode
2016-03-03 Andrew WatermanFix ma_fetch to work with or without RVC
2016-03-03 Andrew WatermanWIP on priv spec v1.9
2015-07-05 Andrew WatermanNew M-mode timers
2015-05-19 Andrew WatermanAdd basic WFI test
2015-05-09 Andrew WatermanUpdate to privileged architecture version 1.7
2015-03-25 Yunsup Leesplit out S-mode tests and M-mode tests
2015-03-25 Andrew WatermanDon't assume PRV1/2 and IE1/2 are reset
2015-03-21 Andrew WatermanMerge rv64si and rv32si tests
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-14 Andrew WatermanAdd PTE dirty bit test
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-02-19 Andrew WatermanUnify rv32/rv64 timer tests
2015-01-10 Andrew WatermanAdd LICENSE
2015-01-05 Andrew WatermanAvoid deprecated "b" pseudo-op; use "j" instead
2014-12-04 Andrew WatermanMake timer test more thorough
2014-05-08 Andrew WatermanAdd timer interrupt test
2014-02-11 Adam IzraelevitzMerge branch 'master' of
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2014-01-31 Andrew WatermanMake CSR test much more robust
2014-01-22 Andrew WatermanAdd CSRRx/CSRRxI test
2013-11-24 Andrew WatermanUpdate to new privileged ISA
2013-08-24 Andrew WatermanReflect changes to ISA
2013-04-24 Yunsup Leecleanup Makefiles in isa
2013-04-22 Yunsup Leeinitial commit