git.libre-soc.org Git - riscv-tests.git/history - isa/rv64sv/illegal_vt

2015-03-25	Yunsup Lee	split out S-mode tests and M-mode tests	blob \| commitdiff \| raw
2015-03-16	Yunsup Lee	revamp vector tests with new privileged spec, and add...	blob \| commitdiff \| raw \| diff to current
2015-01-10	Andrew Waterman	Add LICENSE	blob \| commitdiff \| raw \| diff to current
2013-11-24	Andrew Waterman	Update to new privileged ISA	blob \| commitdiff \| raw \| diff to current
2013-11-06	Yunsup Lee	correctly set SR_EA bit for all vector physical supervi...	blob \| commitdiff \| raw \| diff to current
2013-10-18	Yunsup Lee	add hwacha exception support	blob \| commitdiff \| raw \| diff to current
2013-04-22	Yunsup Lee	initial commit	blob \| commitdiff \| raw \| diff to current