Merge [shm]call into ecall, [shm]ret into eret
[riscv-tests.git] / isa / rv64uf /
2015-03-16 Yunsup Leerevamp vector tests with new privileged spec, and add...
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-02-24 Christopher CelioAdded more +/- NaN/inf tests for fcvt.{w/l/wu/lu}....
2015-02-23 Christopher CelioAdded -NaN test for fcvt.{w/h}.s
2015-02-16 Andrew WatermanMake rv64uf-p-ldst test the sign bit, too
2015-01-10 Andrew WatermanAdd LICENSE
2015-01-05 Andrew WatermanAvoid deprecated "b" pseudo-op; use "j" instead
2014-03-18 Andrew WatermanCheck FP corner cases and flags
2014-03-07 Andrew WatermanAdd fclass.{s|d} test
2013-10-19 Yunsup Leerevamp pt tests as well
2013-10-19 Yunsup Leehwacha virtual tests working
2013-10-17 Yunsup Leeadd passing physical vector tests back in
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Yunsup Leerevamp hwacha tests
2013-08-24 Andrew WatermanReflect changes to ISA
2013-05-02 Andrew Watermanuse RVTEST_RV64UF macro for FPU tests
2013-04-24 Yunsup Leecleanup Makefiles in isa
2013-04-24 Yunsup Leeadd missing RVTEST_CODE_END macros
2013-04-22 Yunsup Leeinitial commit