Don't use stats register; refer to uarch counters by number
[riscv-tests.git] / isa /
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical supervi...
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical tests
2013-10-19 Yunsup Leerevamp pt tests as well
2013-10-19 Yunsup Leehwacha virtual tests working
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-17 Yunsup Leedisable vector bank tests
2013-10-17 Yunsup Leeadd passing physical vector tests back in
2013-10-17 Yunsup Leeupdate out-of-date floating-point test in rv64uv
2013-10-17 Yunsup Leefix broken amoor_w rv64uv test
2013-10-10 Christopher CelioMerge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Yunsup Leerevamp hwacha tests
2013-09-21 Andrew WatermanRe-enable virtual memory tests
2013-09-21 Andrew WatermanNew AUIPC semantics
2013-09-11 Andrew WatermanAdd AMOXOR test
2013-08-25 Andrew Watermandon't emit vvcfg for now
2013-08-24 Andrew WatermanReflect changes to ISA
2013-08-24 Sebastien MiroloMerge pull request #1 from smirolo/configure
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-26 Andrew WatermanRemove JALR static hints
2013-07-24 Sebastien Mirolofeature: add autoconf
2013-06-10 Andrew WatermanDon't disassemble zeros
2013-05-16 Yunsup Leeadd failing multiply test
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-05-02 Andrew Watermanuse RVTEST_RV64UF macro for FPU tests
2013-04-30 Andrew Watermanadd first RV32 tests
2013-04-24 Yunsup Leeadd gitignore
2013-04-24 Yunsup Leecleanup Makefiles in isa
2013-04-24 Yunsup Leeadd missing RVTEST_CODE_END macros
2013-04-24 Yunsup Leeadd more header information to test_macros
2013-04-22 Yunsup Leeinitial commit